Search - clk_div

[File Operate] clk_div

Description: 自己编写的任意分频VHDL程序，程序简单，以供大家分享！-prepare their arbitrary frequency VHDL procedure is simple and for all to share!
Platform: | Size: 34492 | Author: Sea | Hits:

[Other resource] clk_div

Description: vhdl语言描述分频器，实现2、4、8、16……分频，经过实践
Platform: | Size: 36341 | Author: 石仁利 | Hits:

[Other resource] clk_div

Description: VERILOG实现多时钟,可以应用于流水线.输入CLK,输出CLK1,CLK2,CLK3
Platform: | Size: 1392 | Author: kaimen | Hits:

[File Format] clk_div

Description: 自己编写的任意分频VHDL程序，程序简单，以供大家分享！-prepare their arbitrary frequency VHDL procedure is simple and for all to share!
Platform: | Size: 33792 | Author: Sea | Hits:

Description: VHDL实现任意整数分频，--只要把n设置成你要分频的数值就可以了-VHDL arbitrary integer frequency,-- n as long as you want to set the frequency of the numerical breakdown on the
Platform: | Size: 1024 | Author: 赵海东 | Hits:

[VHDL-FPGA-Verilog] clk_div

Description: vhdl语言描述分频器，实现2、4、8、16……分频，经过实践-description language VHDL divider, 2,4,8,16 ... ... realize frequency, through the practice of
Platform: | Size: 35840 | Author: digua | Hits:

[VHDL-FPGA-Verilog] clk_div

Description: VERILOG实现多时钟,可以应用于流水线.输入CLK,输出CLK1,CLK2,CLK3-Verilog realize multi-clock, can be applied to assembly line. Input CLK, the output CLK1, CLK2, CLK3
Platform: | Size: 1024 | Author: kaimen | Hits:

[VHDL-FPGA-Verilog] clk_div.vhd

Description: 实现对时钟信号的技术分频，程序简单易懂，对于初学VHDL者来说，提供了一个良好的方法。-Implementation of the clock signal frequency technology, the program easy to understand, for the beginner who VHDL, provides a good approach.
Platform: | Size: 1024 | Author: 王宇坤 | Hits:

[Multimedia program] CLK_DIV

Description: 爱用硬件描述语言VHDL实现输入时钟10分频输出-divide CLOCK by 10 using VHDL
Platform: | Size: 3072 | Author: 陈绪文 | Hits:

[VHDL-FPGA-Verilog] clk_div

Description: VHDL描述的时钟分频电路，用途广-VHDL description of the clock divider circuit, uses widely ...
Platform: | Size: 1024 | Author: zhan | Hits:

[VHDL-FPGA-Verilog] clk_div

Description: Clock division document
Platform: | Size: 1024 | Author: mangesh.kathale | Hits:

[VHDL-FPGA-Verilog] clk_div

Description: VHDL语言描述，时钟分频,给定CPLD试验板系统时钟设置50M，但由于本作品的需要，我们将系统时钟经过20分频得到DS18B20所需的工作时钟，大约为1.25M。-VHDL language description, the clock frequency, a given CPLD experiment board system clock set 50M, but as a result of this work, we will be the system clock frequency after 20 hours of work needed to be DS18B20 clock, about 1.25M.
Platform: | Size: 161792 | Author: shenqin | Hits:

[VHDL-FPGA-Verilog] clk_div

Description: 一个时钟分频模块,in verilog hdl-clock division module in verilog hdl
Platform: | Size: 1024 | Author: machenghai | Hits:

[VHDL-FPGA-Verilog] DE2

Description: 使用 DE2板制作的多功能数字钟，含有选择功能，秒表，电子表，闹钟，用7-segment LED液晶显示，可以通过LCD看当时状态附有仿真波形--Clk_Div,- Mode_Select,-Watch,-stop_watch,-Lcd_Module,-Total_Out source code，Simulation waveform
Platform: | Size: 3694592 | Author: 赵香君 | Hits:

[VHDL-FPGA-Verilog] clk_div

Description: Clock devider in VHDL code
Platform: | Size: 2048 | Author: Haitham | Hits:

[VHDL-FPGA-Verilog] clk_div

Description: Thia is VHDL code for clock divider
Platform: | Size: 49152 | Author: Marija | Hits:

[VHDL-FPGA-Verilog] clk_div

Description: ＦＰＧＡ　Ｖｒｉｌｏｇ　ＨＤＬ　分频器　输入３３ＭＨＺ　，输出１ＫＨＺ－５０ＨＺ-FPGA Vrilog HDL divider input 33MHZ, output 1KHZ-50HZ
Platform: | Size: 5099520 | Author: 魏杰 | Hits:

[Other] clk_div

Description: 用了20bit的计数器cnt，循环的计数，所以说一个周期有2的20次幂也即大约有1M分频，因为主时钟50MHz（周期就是20ns），所以20ms一个计数周期。蜂鸣器就以20ms的周期性发声，大家可以改变cnt的值看看效果。-quartus clock divided
Platform: | Size: 132096 | Author: 李蒙 | Hits:

[Other] clk_div

Description: 分频计数器verilog源代码,包括实验说明文档,清晰易懂.-this code can easily be understood and teaches you how to divide the clock.
Platform: | Size: 199680 | Author: 颜爱良 | Hits:

[VHDL-FPGA-Verilog] CLK_DIV

Description: 用来产生一个电路的基准的时钟信号，并可以以此为基准产生其他与此时钟信号成倍数时钟信号-Used to generate a reference clock signal circuit and can produce this as a reference clock signal into the other and the clock multiplier
Platform: | Size: 1024 | Author: da | Hits:

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[File Operate] clk_div

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[VHDL-FPGA-Verilog] CLK_DIV

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