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[Other] altclklock

Description: 如何给时钟倍频或者分频，以及altera提供的IP核使用方法-How to clock multiplier or divider, as well as to provide the IP of nuclear altera use
Platform: | Size: 2048 | Author: 杨华 | Hits:

[Embeded-SCM Develop] yifabandaoti

Description: 时钟分频电路实现精讲(19 pages)——意法半导体-Clock divider circuit精讲(19 pages)- STMicroelectronics
Platform: | Size: 90112 | Author: 悠酷男孩 | Hits:

[VHDL-FPGA-Verilog] div_js

Description: 技术分频器。把时钟分为奇数个，好像我做出来是个通用的。-Technology divider. The clock is divided into odd-numbered months, as I make out is a common.
Platform: | Size: 272384 | Author: catalina | Hits:

[VHDL-FPGA-Verilog] freqdivfinal

Description: 用vhdl实现的分频器，可产生任意对主时钟的分频，从而是实现不同频率pwm的控制-Achieved using VHDL divider can produce any of the sub-master clock frequency, thereby achieving different frequency pwm control
Platform: | Size: 2048 | Author: | Hits:

[Windows Develop] clock-divider

Description: 这是一个关于时钟分频率器的程序，它可以实现频率的扩大。-This is a device on the clock frequency of the procedure, it can realize the expansion of the frequency.
Platform: | Size: 1024 | Author: 李军 | Hits:

[VHDL-FPGA-Verilog] clk-div

Description: VHDL code for a clock divider by 27 circuit with a resulting waveform with 50％ duty cycle..
Platform: | Size: 3072 | Author: 李军 | Hits:

[VHDL-FPGA-Verilog] Frequency_divider

Description: 用VERILOG HDL实现的任意 频率分频器源代码，是一个通用的程序-With VERILOG HDL realize arbitrary frequency divider source code, is a generic procedure
Platform: | Size: 134144 | Author: 洪磊 | Hits:

[VHDL-FPGA-Verilog] FPQ

Description: 分频器的vhdl描述，在源代码中完成对时钟信号CLK的2分频,4分频,8分频,16分频-Divider vhdl description of the source code at the completion of the CLK clock signal frequency of 2 hours, 4 minutes frequency, frequency of 8 hours, 16 minutes frequency
Platform: | Size: 1024 | Author: LS | Hits:

[VHDL-FPGA-Verilog] FPGA_nCLK

Description: VHDL语言的高频时钟分频模块。一种新的分频器实现方法。-VHDL language at the high-frequency clock frequency modules. Divider to achieve a new method.
Platform: | Size: 49152 | Author: 李超 | Hits:

[VHDL-FPGA-Verilog] clock_divider

Description: This code contains the simple program that can be used for the clock divider to set any desireable clock from the master clock.
Platform: | Size: 1024 | Author: Shahzad | Hits:

[VHDL-FPGA-Verilog] clock

Description: verilog HDL 编写的时钟分频器-prepared by the clock divider verilog HDL
Platform: | Size: 672768 | Author: luoxs | Hits:

[Other Embeded program] 8253clock

Description: 本实验利用8253做定时器，用定时器输出的脉冲控制8259产生中断 在8259中断处理程序中，对时、分、秒进行计数，在等待中断的循 环中用LED显示时间。 8253用定时器/计数器1，8253片选接CS4，地址为0C000H。8253时钟 源CLK1接分频电路的F/64输出。分频器的Fin接4MHz时钟。8253的 GATE1接VCC。 8259中断INT0接8253的OUT1，片选接CS5，地址为0D000H。 显示电路的KEY/LED CS 接CS0，地址为08000H。-In this study, the use of 8253 to do the timer, using timer pulse output control 8259 generates an interrupt in 8259 interrupt handler, for hours, minutes and seconds count, waiting for interruption through ring using LED display time. 8253 with the timer/counter 1,8253 chip select access CS4, address 0C000H. 8253 clock source CLK1 of the F/64 then divider circuit output. Fin then 4MHz clock divider. 8253' s GATE1 then VCC. 8259 interrupt INT0 then 8253' s OUT1, chip select access CS5, address 0D000H. Display circuit of the KEY/LED CS access CS0, address 08000H.
Platform: | Size: 2048 | Author: 夏伟 | Hits:

[VHDL-FPGA-Verilog] divider

Description: a clock divider vhdl code
Platform: | Size: 236544 | Author: mansih | Hits:

[VHDL-FPGA-Verilog] Downloads

Description: clock divider in verilog for FPGA use
Platform: | Size: 1024 | Author: harini | Hits:

[VHDL-FPGA-Verilog] clock_divider

Description: clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc-clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc
Platform: | Size: 8192 | Author: sreejith | Hits:

[VHDL-FPGA-Verilog] clock-divider

Description: VHDL code for clock divider circuit. There are two modules: one output divide by 4 and other outputs divide by 6
Platform: | Size: 1024 | Author: zpatel | Hits:

[Algorithm] Clock-Divider

Description: this verilog program, Clock Divider, can be compiled successfully by Altera and ModelSIM.
Platform: | Size: 155648 | Author: anxar | Hits:

[Other] clock

Description: there's a clock divider for DE2 altra board clock (50MHz)
Platform: | Size: 623616 | Author: hosseinkhani | Hits:

[Other] RPWM-matlab

Description: clock divider program by using VHDL
Platform: | Size: 869376 | Author: muthukumarvlsi | Hits:

[VHDL-FPGA-Verilog] clock divider example

Description: this is clock divider example code
Platform: | Size: 755 | Author: prabhu | Hits:
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