Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: FPGA_nCLK Download
 Description: VHDL language at the high-frequency clock frequency modules. Divider to achieve a new method.
 Downloaders recently: [More information of uploader xdlc416]
 To Search: clock divider vhdl
  • [9.7_DIRIVER_control] - based on Verilog-HDL hardware Circuit of
  • [freqdivfinal] - Achieved using VHDL divider can produce
  • [f50k] - VHDL generated clock frequency of 50 pro
  • [fenpin] - This is the design of the divider module
File list (Check if you may need any files): 
基于FPGA的高频时钟的分频和分配设计.doc

CodeBus www.codebus.net