Description: This is the design of the divider module EDA. Can achieve three different frequency signals, users can freely set the frequency of the size of
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- [as] - This is Assmbler command document as
- [FPGA_nCLK] - VHDL language at the high-frequency cloc
File list (Check if you may need any files):
fenpin
......\automake.log
......\coregen.log
......\coregen.prj
......\fenpin.dhp
......\fenpin.npl
......\fenpin1.ldo
......\fenpin1.spl
......\fenpin1.sym
......\fenpin1.vhdl
......\fenpin1_tbw_vhd_tb.fdo
......\fenpin1_tbw_vhd_tb.udo
......\fenpin1_test_vhd_tb.fdo
......\fenpin1_test_vhd_tb.udo
......\pepExtractor.prj
......\results.txt
......\tbw.tbw
......\tbw.vhd
......\test.vhd
......\transcript
......\vsim.wlf
......\wave.ANT
......\wave.fdo
......\wave.jhd
......\wave.tbw
......\wave.udo
......\wave.vhw
......\work
......\....\fenpin1
......\....\.......\behavioral.asm
......\....\.......\behavioral.dat
......\....\.......\_primary.dat
......\....\fenpin1_cfg
......\....\...........\_primary.dat
......\....\...........\_vhdl.asm
......\....\fenpin1_tbw_vhd_tb
......\....\..................\behavior.asm
......\....\..................\behavior.dat
......\....\..................\_primary.dat
......\....\fenpin1_test_vhd_tb
......\....\...................\behavior.asm
......\....\...................\behavior.dat
......\....\...................\_primary.dat
......\....\wave
......\....\....\testbench_arch.asm
......\....\....\testbench_arch.dat
......\....\....\_primary.dat
......\....\_info
......\xst
......\...\work
......\...\....\hdllib.ref
......\...\....\hdpdeps.ref
......\...\....\sub00
......\...\....\.....\vhpl00.vho
......\...\....\.....\vhpl01.vho
......\__projnav
......\.........\coregen.rsp
......\.........\fenpin.gfl
......\.........\hb_cmds
......\__projnav.log
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