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[DSP program] quartusII_clock

Description: vhdl语言开发，开发环境为QuartusII6.0和NIOS 6.0开发，是一个模拟交通灯的程序，其中用的芯片是stratix系列-vhdl language development, QuartusII6.0 development environment for the development and NIOS 6.0, is a simulated traffic signals procedures, which the chip is stratix Series
Platform: | Size: 7562240 | Author: 河南 | Hits:

[SCM] ds1337_nios

Description: 时钟芯片ds1337在嵌入式处理器nios上的底层驱动程序-Clock Chip ds1337 Nios embedded processor in the underlying drivers
Platform: | Size: 1024 | Author: xjtualaddin | Hits:

[Embeded-SCM Develop] blank_project_0

Description: 在nios II DE2开发板上开发的实时时钟，已经测试通过-In nios II DE2 development board developed by real-time clock has been tested through
Platform: | Size: 3072 | Author: 沈克镇 | Hits:

[ARM-PowerPC-ColdFire-MIPS] Altera

Description: 利用Nios Ⅱ软核处理器，以Altera公司的UP3开发板为硬件平台，以Quartus II、Quartus ID为软件开发平台，设计一个电子钟，实现下列系统功能： （1）在液晶屏上显示时间、日期、状态提示； （2）利用4个按键对时间（时分秒）、日期（年月日）进行设置； （3）利用一个LED灯指示当前设置状态；-The use of soft-core processor, Nios Ⅱ to Altera s UP3 development board as the hardware platform to Quartus II, Quartus ID for software development platform, design a clock
Platform: | Size: 6460416 | Author: Emma | Hits:

[VHDL-FPGA-Verilog] NIOSII_tutorial_code

Description: NIOSII实例代码。包括系统时钟代码，DMA(Memory to Memory)驱动代码，Fine-gained Flash Access驱动代码,Timestamp驱动代码,ISR代码，Simple Flash Access驱动代码，UART代码-NIOSII examples of code. Including the system clock source, DMA (Memory to Memory) drive code, Fine-gained Flash Access driver code, Timestamp-driven code, ISR code, Simple Flash Access driver code, UART code
Platform: | Size: 8192 | Author: danielmu | Hits:

[VHDL-FPGA-Verilog] 15NIOSIIclock

Description: nios num clock verilog code
Platform: | Size: 378880 | Author: dan | Hits:

[Other] CLOCK

Description: 文通过ALTERA公司的quartus II软件，用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为：计时功能，24小时制计时显示；通过七段数码管动态显示时间；校时设置功能，可分别设置时、分、秒；跑表的启动、停止 、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital clock. The main function of the completion are: time function, 24-hour time display through the Seven-Segment LED dynamic display time school settings function, can be set hours, minutes, seconds the stopwatch to start, stop, and maintain display and removal.
Platform: | Size: 182272 | Author: 张保平 | Hits:

[SCM] ds1302

Description: 这是一个使用了DS1302的电子时钟C程序，文档里含有DS1302的操作说明资料，以及PROTEUS仿真,例外还有一个外加LCD显示和温度检测的程序-This is a DS1302 using the electronic clock C procedures DS1302 document contains information on the operating instructions, as well as the PROTEUS simulation, with the exception of a LCD display and temperature in addition to testing procedures
Platform: | Size: 1312768 | Author: liuwei | Hits:

[VHDL-FPGA-Verilog] lcd

Description: Nios II驱动ocmj4X8c液晶的程序 时钟50M-Nios II-driven process ocmj4X8c LCD clock 50M
Platform: | Size: 1024 | Author: 刘毅冰 | Hits:

[Other] NIOS

Description: 北航的NIOSII教程！！第7章 Nios Ⅱ嵌入式处理器设计 7.1 Nios Ⅱ嵌入式处理器简介 7.2 Nios Ⅱ嵌入式处理器软、硬件开发流程 7.3 Nios Ⅱ嵌入式处理器系统的开发 7.4 Nios Ⅱ嵌入式处理器外围接口 7.5 HAL系统库 7.6 设计实例——电子钟 -Beihang' s NIOSII tutorial! ! Chapter 7 Nios Ⅱ embedded processor embedded processor design 7.1 Nios Ⅱ Introduction 7.2 Nios Ⅱ embedded processor hardware and software development processes 7.3 Nios Ⅱ embedded processor system development 7.4 Nios Ⅱ embedded processor Peripheral Interface 7.5 HAL System Library 7.6 Design Example- E-Clock
Platform: | Size: 2739200 | Author: 殷桃 | Hits:

[VHDL-FPGA-Verilog] NIOS_I2C_SD2405

Description: 基于NIOS的I2C总线，SD2405实时时钟芯片读写代码。-I2C-bus based NIOS, SD2405 real-time clock chip to read and write code.
Platform: | Size: 7168 | Author: ZZ | Hits:

[VHDL-FPGA-Verilog] NIOS_I2C_SD2405_AT24C128

Description: 基于NIOS的I2C总线，AT24C128和SD2405实时时钟芯片混合编程驱动。在I2C地址选择处有经典用法！-I2C-bus based NIOS, AT24C128, and SD2405 hybrid programming driven real time clock chip. I2C address selection in the Department has the classic usage!
Platform: | Size: 7168 | Author: ZZ | Hits:

[VHDL-FPGA-Verilog] nios_shi

Description: 由nios ii实现的，用cfi flash与SDRAM共同实现的电子数字时钟，基于sopc的嵌入式代码，所用软件都是9.0版本的，包括quartus ii9.0 和nios ii9.0-Achieved by the nios ii, together with the cfi flash with SDRAM to achieve the electronic digital clock, based on sopc embedded code, the software is version 9.0, including quartus ii9.0, and nios ii9.0
Platform: | Size: 8524800 | Author: liyu | Hits:

[VHDL-FPGA-Verilog] nios_dds

Description: 采用Altera的NIOS内核，配合独立的累加器，实现了正弦波，三角波，锯齿波和方波的DDS产生电路，系统时钟最高可达120MHz，配合高速DAC，可产生最高约40MHz左右的波形-Using Altera' s NIOS core, with a separate accumulator, to achieve a sine wave, triangle wave, sawtooth and square wave generation circuit DDS system clock up to 120MHz, with high-speed DAC, can produce up to about 40MHz waveform around
Platform: | Size: 3113984 | Author: Tomy Lee | Hits:

[SCM] digitalelectricalclockdesignbasedonNIOSII

Description: ：以NiosⅡ Cyclone EPIC20F400C7开发板为硬件平 台，利用 Ouartus II、SOPC Builder和 NiosⅡIDE软件设计来实 现一个基于 SOPC的多功能数字电子钟-: The Nios Ⅱ Cyclone EPIC20F400C7 development board as the hardware platform, using Ouartus II, SOPC Builder and Nios Ⅱ IDE to implement a software design based on multi-purpose digital electronic clock SOPC
Platform: | Size: 222208 | Author: 裴蕾 | Hits:

[VHDL-FPGA-Verilog] 110819_1

Description: 基于sopc的lcd时钟，开发工具为nios ii和quartus ii9.0-Based on sopc the lcd clock, development tools for the nios ii and quartus ii9.0
Platform: | Size: 6258688 | Author: | Hits:

[VHDL-FPGA-Verilog] tlc7528

Description: 基于NIOS核，实现对TI的tlc7528时钟芯片进行操作，实现计时-Based on NIOS core, TI s tlc7528 achieve clock chip operation, to achieve timing
Platform: | Size: 8600576 | Author: 郎平 | Hits:

[VHDL-FPGA-Verilog] IS61WV51232BLL

Description: 这是SRAM-IS61WV51232BLL在NIOS软核应用下的读写时许代码。-This is SRAM-IS61WV51232BLL under NIOS soft-core application code reader o' clock.
Platform: | Size: 2048 | Author: 谭松清 | Hits:

[VHDL-FPGA-Verilog] Nios_Clock

Description: FPGA平台下基于Nios II的数字闹钟的源程序，从DS1302读取时钟数据，在LCD12864上显示出来，按键控制闹钟设定，蜂鸣器闹铃。-Digital clock Nios II source program based on the FPGA platform, clock read data from the DS1302, in the LCD12864 display, keyboard control alarm, buzzer alarm.
Platform: | Size: 12622848 | Author: 光速不变 | Hits:

[VHDL-FPGA-Verilog] clock-for-nios

Description: 基于niosⅡ的数字钟设计，适用于多种FPGA的开发板，修改管脚可移植。-NiosⅡ digital clock design is based on, for a variety of FPGA development board, modify pin portable.
Platform: | Size: 422912 | Author: 李悦 | Hits:
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