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[VHDL-FPGA-Verilogfdpll

Description: 简单的可配置dpll的VHDL代码。 用于时钟恢复后的相位抖动的滤波有很好的效果, 而且可以参数化配置pll的级数。-simple configurable dpll VHDL code. Clock Recovery for the jitter filtering is a very good result, but can pll configuration parameters of the series.
Platform: | Size: 2048 | Author: 陈德炜 | Hits:

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