Description: simple configurable dpll VHDL code. Clock Recovery for the jitter filtering is a very good result, but can pll configuration parameters of the series.
- [DPLL.Rar] - digital phase-locked loop PLL design sou
- [8octavevhdl] - the document available VHDL Language 8 c
- [dpll0227] - DPLL simultaneously extract a certain ef
- [clkrecoveryDPLL] - Clock recovery for all-digital phase-loc
- [DIGTAL_FIR] - Loop filter design, FPGA-based PLL appli
- [dpll] - FPGA realization of all-digital phase-lo
- [ADI_pll_Set] - VHDL prepared ADI PLL control procedures
- [shift] - E1 to receive some of the major function
- [clock] - By the phase-locked loop (PLL) have the
- [NCO_sin] - The VHDL code of VCO
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