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Title: clock Download
 Description: By the phase-locked loop (PLL) have the necessary 2-and 4-frequency clock frequency of 8 minutes for Executable clk.qpf main clock
 Downloaders recently: [More information of uploader jichuanlu]
 To Search: PLL VHDL
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  • [fdpll] - simple configurable dpll VHDL code. Cloc
  • [verilogpll] - using Verilog language prepared by the D
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File list (Check if you may need any files):
clock
.....\clk.asm.rpt
.....\clk.done
.....\clk.eda.rpt
.....\clk.fit.rpt
.....\clk.fit.smsg
.....\clk.fit.summary
.....\clk.flow.rpt
.....\clk.map.rpt
.....\clk.map.summary
.....\clk.pin
.....\clk.pof
.....\clk.ppf
.....\clk.qpf
.....\clk.qsf
.....\clk.qws
.....\clk.sim.rpt
.....\clk.sof
.....\clk.tan.rpt
.....\clk.tan.summary
.....\clk.v
.....\clk.vwf
.....\clk_bb.v
.....\clock_gen.bdf
.....\db
.....\..\clk.asm.qmsg
.....\..\clk.cbx.xml
.....\..\clk.cmp.cdb
.....\..\clk.cmp.hdb
.....\..\clk.cmp.kpt
.....\..\clk.cmp.logdb
.....\..\clk.cmp.rdb
.....\..\clk.cmp.tdb
.....\..\clk.cmp0.ddb
.....\..\clk.dbp
.....\..\clk.db_info
.....\..\clk.eco.cdb
.....\..\clk.eda.qmsg
.....\..\clk.eds_overflow
.....\..\clk.fit.qmsg
.....\..\clk.hier_info
.....\..\clk.hif
.....\..\clk.map.cdb
.....\..\clk.map.hdb
.....\..\clk.map.logdb
.....\..\clk.map.qmsg
.....\..\clk.pre_map.cdb
.....\..\clk.pre_map.hdb
.....\..\clk.psp
.....\..\clk.rtlv.hdb
.....\..\clk.rtlv_sg.cdb
.....\..\clk.rtlv_sg_swap.cdb
.....\..\clk.sgdiff.cdb
.....\..\clk.sgdiff.hdb
.....\..\clk.signalprobe.cdb
.....\..\clk.sim.hdb
.....\..\clk.sim.qmsg
.....\..\clk.sim.rdb
.....\..\clk.sim.vwf
.....\..\clk.sld_design_entry.sci
.....\..\clk.sld_design_entry_dsc.sci
.....\..\clk.syn_hier_info
.....\..\clk.tan.qmsg
.....\..\wed.zsf
.....\simulation
.....\..........\modelsim
.....\..........\........\clk.vo
.....\..........\........\clk_modelsim.xrf
.....\..........\........\clk_v.sdo
.....\说明文档.txt
    

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