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[Other resource] chengxu(vhdl)

Description: 这是用VHDL编写的FPGA与计算机进行串口通信的程序和一个LED程序-VHDL and FPGA prepared by the computer serial communication procedures and an LED procedures
Platform: | Size: 549372 | Author: 黄鹏飞 | Hits:

[VHDL-FPGA-Verilog] 用VHDL语言在CPLD上实现串行通信

Description: 用VHDL语言在CPLD上实现串行通信-using VHDL on the CPLD Serial Communication
Platform: | Size: 4096 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] 标准的串口通讯设计VHDL

Description: 标准的异步串口通讯设计程序——基于VHDL编程-communication design programme of standard asynchronous serial port base on VHDL programme
Platform: | Size: 10240 | Author: 于飞 | Hits:

[VHDL-FPGA-Verilog] chengxu(vhdl)

Description: 这是用VHDL编写的FPGA与计算机进行串口通信的程序和一个LED程序-VHDL and FPGA prepared by the computer serial communication procedures and an LED procedures
Platform: | Size: 548864 | Author: 黄鹏飞 | Hits:

[VHDL-FPGA-Verilog] CUS_SPI-VHDL

Description: 此为VHDL的SPI通信代码，全部在一个压缩包中，请仔细阅读后再使用．-this as VHDL code SPI communication, all in a compressed package, please read carefully before use.
Platform: | Size: 4096 | Author: 藏瑞 | Hits:

[VHDL-FPGA-Verilog] uart-verilog-vhdl

Description: 拿verilog和vhdl编写的串口通信代码(可综合)-with vhdl and verilog prepared by the serial communication code (synthesis)
Platform: | Size: 294912 | Author: 刘索山 | Hits:

[VHDL-FPGA-Verilog] PulseWidth_detector_VHDL

Description: 通信控制中常用的脉冲宽度检测程序，VHDL模块化编成实现（原创）-communication control used in pulse width detection procedures, VHDL modular organization to achieve (original)
Platform: | Size: 1024 | Author: 汤维 | Hits:

[VHDL-FPGA-Verilog] FPGA-SD-COMMUNICATION

Description: 基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信 所用语言位verilog HDL-QUARTUSII software implementation based on FPGA (ATERA CYCLONE II series) with SD Card SD mode digital communication language verilog HDL
Platform: | Size: 5064704 | Author: chenbinjie | Hits:

[Com Port] uart

Description: 采用CPLD实现串口通信（Verilog硬件描述语言）-Realize the use of CPLD serial communication (Verilog Hardware Description Language)
Platform: | Size: 5120 | Author: wuzhidong | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 伪随机码发生器的VHDL实现 随着通信理论的发展，早在20世纪40年代，香农就曾指出，在某些情况下，为了实现最有效的通信，应采用具有白噪声的统计特性的信号。另外，为了实现高可靠的保密通信，也希望利用随机噪声。然而，利用随机噪声最大困难是它难以重复产生和处理。直到60年代，伪随机噪声的出现才使这一难题得到解决-Pseudo-random code generator for VHDL realize communication with the development of the theory, as early as the 20th century, 40 years, Shannon has pointed out that in some cases, in order to realize the most effective communications, should be used with the statistical properties of white noise signal . In addition, in order to realize highly reliable secure communication, but also wish to take advantage of random noise. However, the use of random noise the greatest difficulty is that it difficult to repeat the generation and treatment. Until 60 years, the emergence of pseudo-random noise so that this problem only be solved
Platform: | Size: 217088 | Author: 张之晗 | Hits:

[VHDL-FPGA-Verilog] VHDL-SPI-Module.doc

Description: 本spi参数化通讯模块是一个支持SPI串行通信协议从协议的SPI从接口。可通过改变参数设置传输的位数，由外部控制器给定脉冲控制传输。-The parameters of spi communication module is a support SPI serial communication protocol from the agreement from the SPI interface. By changing the parameter settings can be transmitted over the median, given by an external controller to control transmission pulse.
Platform: | Size: 37888 | Author: | Hits:

[ARM-PowerPC-ColdFire-MIPS] DesignofIntegratedCircuitsforOpticalCommunications

Description: Design of Integrated Circuits for Optical Communications deals with the design of high-speed integrated circuits for optical communication systems. Written for both students and practicing engineers, the book systematically takes the reader from basic concepts to advanced topics, establishing both rigor and intuition. The text emphasizes analysis and design in modern VLSI technologies, particularly CMOS, and presents numerous broadband circuit techniques. Leading researcher Behzad Razavi is also the author of Design of Analog CMOS Integrated Circuits. -Design of Integrated Circuits for Optical Communications deals with the design of high-speed integrated circuits for optical communication systems. Written for both students and practicing engineers, the book systematically takes the reader from basic concepts to advanced topics, establishing both rigor and intuition. The text emphasizes analysis and design in modern VLSI technologies, particularly CMOS, and presents numerous broadband circuit techniques. Leading researcher Behzad Razavi is also the author of Design of Analog CMOS Integrated Circuits.
Platform: | Size: 10731520 | Author: huang | Hits:

[VHDL-FPGA-Verilog] uart8

Description: 使用Libero提供的异步通信IP核实现UART通信，并附带仿真程序。UART设置为1位开始位，8位数据位，1位停止位，无校验。且UART发送自带2级FIFO缓冲，占用FPGA面积很小。-Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to start bit, 8 data bits, 1 stop bit, no parity. UART and send its own two FIFO buffer occupancy is very small FPGA.
Platform: | Size: 876544 | Author: 张键 | Hits:

[Embeded-SCM Develop] RS232.VHDL

Description: RS232 Communication function in VHDL for Spartan 3E
Platform: | Size: 1024 | Author: Tony Tan | Hits:

[VHDL-FPGA-Verilog] adaptive_lms_equalizer_latest.tar

Description: In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear. and more sevear is such distortion is random. To handle this, multipath affected channels require Equalizers at receaver end. such equalizer uses different learning Algorithms for identifying channels continuously. This project is VHDL implementation of LMS learning algorithm with pipelined architecture. so this implementation can work with higher data rates with less clock speed requirments and so with less power consumpiton It uses Fixed point arithmatic blocks for filtering so suitable for coustom asic.
Platform: | Size: 14336 | Author: Arun | Hits:

[VHDL-FPGA-Verilog] hilbert_transformer_latest.tar

Description: The Hilbert Transform is an important component in communication systems, e.g. for single sideband modulation/demodulation, amplitude and phase detection, etc. It can be formulated as filtering operation which makes it possible to approximate the Hilbert Transform with a digital filter. Due to the non-causal and infinite impulse response of that filter, it is not that easy to get a good approximation with low hardware resource usage. Therefore, different filters with different complexities have been implemented. The detailed discussion can be found in "Digital Hilbert Transformers or FPGA-based Phase-Locked Loops" (http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4629940). The design is fully pipelined for maximum throughput.
Platform: | Size: 1239040 | Author: Arun | Hits:

[File Format] 17bit_Smart_Absolute_Encoder

Description: 多摩川17bit绝对值编码器的NRG协议文档，配合上传的解码源程序，采用半双工的通信模式。-Tamagawa 17bit absolute encoder NRG agreement documents, with the upload source decoder, using half-duplex communication mode.
Platform: | Size: 4419584 | Author: 王中超 | Hits:

[Software Engineering] RAKE_FPGA

Description: RAKE技术与CDMA系统相结合，能够带来系统容量和通信质量的极大提 高。根据军事通信中对设备便携性及低功耗的特殊要求，本文研究了一种便携式 基站的收发系统，重点研究了其中的RAKE接收部分。给出了系统的发送方案和 接收方案，对接收机部分所涉及的关键技术和算法，包括数字下变频技术、匹配相关技术、多径搜索技术、信道估计技术、解调及多径合并技术进行了较为详细的分析和说明。在此基础上，运用VHDL语言进行了硬件平台上FPGA部分的功能实现，并对整个系统进行了调试，给出了一些相关的仿真及测试结果。最后对该系统还需进一步研究的问题进行了简要的介绍，对调试过程中的出现的一些问题进行了简单的分析和小结。 -CDMA system with RAKE combining technology, can bring the system capacity and communication quality significantly raised High. According to military communications equipment portability and low power consumption special requirements, this paper, a portable The base station transceiver system, which focuses on the RAKE receiving part. Then the system sends the program and Receiving scheme, the receiver part of the key technologies involved and algorithms, including digital down-conversion technology, matching the relevant technology, multi-path search and channel estimation, demodulation and multi-path merging techniques on a more detailed analysis and explanation. On this basis, the use of VHDL, FPGA hardware platform to achieve some functionality, and debugging the system, given some of the relevant simulation and test results. Finally the system need further study are briefly introduced, and the emergence of the process of debugging some problems in a simple analysis and summar
Platform: | Size: 2499584 | Author: 徐进 | Hits:

[VHDL-FPGA-Verilog] RS232

Description: RS232 串口通信 的 VHDL描述，初学FPGA的朋友可以-RS232 serial communication VHDL description, FPGA beginner friends can see
Platform: | Size: 1346560 | Author: chengwenfan | Hits:

[VHDL-FPGA-Verilog] infrared-communication-IP

Description: Altera University Program for infrared communication IP
Platform: | Size: 483328 | Author: sjdbjs | Hits:
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