Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - compare verilog

Search list

[Software Engineering] pld

Description: 利用QuartusII的"MegaWizard Plug-In Manager", 设计输入数据宽度是4bit的ADD、SUB、MULT、DIVIDE、COMPARE 把它们作为一个project,DEVICE选用EPF10K70RC240-4，对它们进行 时序仿真，将仿真波形（输入输出选用group）在一页纸上打印出来。 2.利用QuartusII的"MegaWizard Plug-In Manager"中的LPM_COUNTER， 设计一个20bit的up_only COUNTER, 要求该COUNTER在FE0FA和FFFFF之间自动循环计数； 分析该COUNTER在EPM7128SLC84-7、EPM7128SLC84-10、和EPF10K70RC240-2、 EPF10K70RC240-4几种芯片中的最大工作频率； 请将计数器的输出值在FFFFC--FE0FF之间的仿真波形打印出来 （仅EPF10K70RC240-4芯片,最大允许Clock频率下）。-QuartusII use the MegaWizard Plug-In Manager , the design of the input data width is 4bit the ADD, SUB, MULT, DIVIDE, COMPARE them as a project, DEVICE selected EPF10K70RC240-4, on their timing simulation, the simulation waveform (input output selected group) in a paper print out. 2. QuartusII use the MegaWizard Plug-In Manager in LPM_COUNTER, the design of a 20bit of up_only COUNTER, requested that the COUNTER in FE0FA and automatic cycle count between FFFFF analysis of the COUNTER in EPM7128SLC84-7, EPM7128SLC84-10, and EPF10K70RC240-2, EPF10K70RC240-4 Several of the largest chip operating frequency I would be grateful if the output value of counter FFFFC- FE0FF simulation waveform between the print out (only EPF10K70RC240-4 chips, the maximum allowable Clock frequency).
Platform: | Size: 31744 | Author: 李侠 | Hits:

[VHDL-FPGA-Verilog] ALU

Description: 算术逻辑部件的verilog代码，它能够实现半加器、全加器、比较、按位与、按位或、按位异或、加一、减一的操作-Arithmetic logic unit of the verilog code, it can achieve half adder, full adder, compare, bitwise and, bitwise or, bitwise xor, plus one, minus one operation
Platform: | Size: 169984 | Author: 李鹏飞 | Hits:

[VHDL-FPGA-Verilog] compare

Description: 一个用verilog写的基本的比较器，其中带了一些其他的电路，也是用verilog编的，希望对读者有用。-Use verilog to write a basic comparator, which brought a number of other circuits, but also with the verilog code, and I hope useful to readers.
Platform: | Size: 125952 | Author: lixu | Hits:

[VHDL-FPGA-Verilog] compare

Description: Verilog实现的比较器，内含全部源码。-Comparators implemented Verilog, containing all the source code.
Platform: | Size: 136192 | Author: qinmingmin | Hits:

[VHDL-FPGA-Verilog] cookbook

Description: 用于verilog入门的小程序，包括各种crc,compare等常用硬件电路的描述-verilog cookbook，including several verilog code of crc，compare circuit etc.
Platform: | Size: 3442688 | Author: alice | Hits:

[VHDL-FPGA-Verilog] ass1_2_hamming

Description: Hamming codes are a class of binary linear codes. They can detect up to two simultaneous bit errors, and correct single-bit errors. In particular, a single-error-correcting and double error detecting variant commonly referred to SECDED.-a) Develop a Verilog module that will generate a 7-bit encoded data from a 4-bit data. Simulate your design for two inputs. Use even or odd parity according to the least significant figure of your ID number. b) Develop a Veriog module for generating pseudorandom 4-bit data using Linear Feedback Shift Register( LFSR) method. c) Develop a Verilog module to emulate one bit error in the data transmission. This can be done by changing only one of the encoded bits at each clock cycle. You may use a ring-counter and XOr gates for doing this. This arrangement will insert error in consecutive bits at each clock cycle. d) Design a Hamming error detection and correction circuit to restore the original data. e) Compare the original data with the restored data to verify the error correction capability of your design. If the two data sets are equal an OK signal will be set.
Platform: | Size: 1133568 | Author: wei chenghao | Hits:

[VHDL-FPGA-Verilog] datacompare

Description: 采用verilog语言来进行数据比较器 附带仿真波形-Verilog language used to compare data with simulation waveform control
Platform: | Size: 1150976 | Author: allen-haha | Hits:

[VHDL-FPGA-Verilog] Verilog

Description: verilog参考例子，有简单的compare，有时序电路，源代码和仿真-examples using verilog
Platform: | Size: 268288 | Author: 王一小 | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: 几种verilog乘法器的代码，用于比较不同乘法器特点-Several multiplier verilog code, used to compare the different characteristics of the multiplier
Platform: | Size: 10240 | Author: 马力维 | Hits:

[VHDL-FPGA-Verilog] compare

Description: 比较器，四位的比较器，verilog的语言编写的，可以用-The comparator, the comparator four, Verilog language, can be used
Platform: | Size: 244736 | Author: hx | Hits:

[VHDL-FPGA-Verilog] compare

Description: verilog两个数的比较，由加法器改编而来-verilog comparison
Platform: | Size: 1024 | Author: 贺恩力 | Hits:

[VHDL-FPGA-Verilog] compare

Description: 数值比较器的设计，课堂作业随堂检查，verilog语言设计，开发工具是quartus II7.0以上版本，测试仿真脚本也有-Numerical comparison of the design, classwork class check the Verilog language design, development tools is quartus II7.0 above test simulation script
Platform: | Size: 256000 | Author: 刘玉海 | Hits:

[Other] compare

Description: 三个数的比较，输出最大值，Verilog实现，已经建立modelsim工程，可以直接观看波形， Verilog 最大值，fpga-Verilog max value
Platform: | Size: 16384 | Author: 刘勇 | Hits:

[VHDL-FPGA-Verilog] ALU

Description: verilog编写，八位ALU，加减与或比较-verilog prepared eight ALU, subtract, or compare with
Platform: | Size: 2048 | Author: 姬成 | Hits:

[VHDL-FPGA-Verilog] alu

Description: 32位alu模块实现加减法、逻辑运算、移位、比较和置高位立即数等功能。verilog实现。-32-bit alu module achieves functions like addition and subtraction, logical operations, shift, compare, and set a high immediate number by verilog
Platform: | Size: 907264 | Author: sherlydunn | Hits:

[VHDL-FPGA-Verilog] t2_manchester_coder

Description: Manchester 编码器的Verilog与VHDL实现，并分别采用moore和mealy机对其进行描述，比较了两种实现方法的不同。并且每种情况都给出了测试脚本，希望对您有用。-Manchester encoder Verilog and VHDL realization and moore and mealy machines were used to describe it, compare the two implementations of different methods. And in each case are given a test script, I hope useful to you.
Platform: | Size: 155648 | Author: 宋国志 | Hits:

[Other systems] tlc549adc

Description: 使用verilog编写的利用状态机实现对TLC549的采样控制，实验时可调节电位器，改变ADC 的模拟量输入值，数据采集读取后在数码管上显示。可以自己用万用表测一下输入电压， 然后与读取到的数据比较一下。-Use verilog prepared using the state machine to achieve the TLC549 sampling control, adjustable potentiometer experiment, change ADC The analog input value, after reading the data collected on the digital display. You can own what the input voltage measured with a multimeter, Then compare the read data.
Platform: | Size: 230400 | Author: wangyan | Hits:

[Other] compare

Description: 用Verilog HDL编写的简单的比较器-A simple comparator programmed by Verilog Hdl
Platform: | Size: 45056 | Author: 张娜 | Hits:

[VHDL-FPGA-Verilog] compare

Description: 用verilog实现文件输入的比较器，如果同一时间输入的数据相同则输出高电平，否则输出低电平，达到比对的效果。-Use verilog implementation file input comparator, if the input data at the same time the same output high level, otherwise the output low level, to achieve the effect of alignment.
Platform: | Size: 1024 | Author: 孙金傲 | Hits:

[VHDL-FPGA-Verilog] FPGAcode

Description: verilog HDL语言编程实现比较、分频、除法、阻塞与非阻塞语句的源文件和test文件-compare, division,half_clock,block and unblock
Platform: | Size: 4096 | Author: wxy | Hits:

CodeBus www.codebus.net