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[Other resource] complex

Description: 时钟，信号灯verilog for FPGA
Platform: | Size: 3583084 | Author: zhaog gang | Hits:

[VHDL-FPGA-Verilog] VHDL语言100例详解

Description: VHDL语言100例详解。详细讲解了用VHDL语言进行数字电路和数字系统设计的知识。用100个实例，不仅进行基础的门电路设计，而且还有较为复杂的数字系统设计。这些实例可以直接被调用。-VHDL Elaborates on 100 cases. Detailed account of VHDL for digital circuits and digital systems design knowledge. With 100 examples, not only for infrastructure gate design, but also more complex digital system design. These examples can be called.
Platform: | Size: 6633472 | Author: 穆群生 | Hits:

[Other] ahb_system_generator.tar

Description: An AHB system is made of masters slaves and interconnections. A general approach to include all possible "muxed" implementation of multi layered AHB systems and arbitrated AHB ones can be thought as an acyclic graph where every source node is a master, every destination node is a slave and every internal node is an arbiter there must be one and only one arc exiting a master and one or more entering a slave (single slave verus multi-slave or arbitrated slave) an arbiter can have as many input and output connections as needed. A bridge is a special node that collapses one or more slave nodes and a master node in a new "complex" node.
Platform: | Size: 269312 | Author: 木石 | Hits:

[VHDL-FPGA-Verilog] complex

Description: 时钟，信号灯verilog for FPGA -Clock signal verilog for FPGA
Platform: | Size: 3582976 | Author: zhaog gang | Hits:

[VHDL-FPGA-Verilog] DSP

Description: 从算法设计到硬线逻辑的实现：复杂数字逻辑系统的Verilog HDL设计技术和方法，结合DSP算法介绍verilog HdL 设计。-From algorithm design to achieve hard-wired logic: complex digital logic system Verilog HDL design techniques and methods, combined with DSP algorithm design verilog HdL introduced.
Platform: | Size: 3232768 | Author: 李立 | Hits:

[Software Engineering] DDCFPGA

Description: 针对DVB-T标准ETSI EN 300 744 V1.5.1,设计了可用于DVB-T接收整机的多速率DDC模块,并在FPGA中仿真实现.在复用数字振荡混频模块的基础上,根据输入信号的不同带宽(6M/8MHz)选择不同的抽取滤波器组完成抽取因子为3或4的多速率处理任务,利用两级半带滤波器(HBF)级联完成4倍抽取滤波,单级奈奎斯特滤波器完成3倍抽取滤波.-For the DVB-T standard ETSI EN 300 744 V1.5.1, designed for DVB-T receiver machine multi-rate DDC module, and the simulation in the FPGA implementation. Numerical oscillation in the complex mixer module, based on the input signals of different bandwidths (6M/8MHz) choose a different group of complete decimation filter extracted factor 3 or 4 of the multi-rate processing tasks, using two half-band filter (HBF) cascade to complete four times decimation filter, single-stage Chennai Nyquist filter to complete three times the decimation filtering.
Platform: | Size: 309248 | Author: 王楚宏 | Hits:

[VHDL-FPGA-Verilog] FastCplxMuply

Description: This zip folder contains the verilog code for fast complex multiplication source code and its test bench
Platform: | Size: 1024 | Author: Jaganathan | Hits:

[VHDL-FPGA-Verilog] Verilog

Description: 通过本文章的学习能够使我们设计一些简单的逻辑电路和系统。很快我们就能过渡到设计相当复杂的数字逻辑系统。-To learn through this article, will enable us to design some simple logic circuits and systems. Soon we will be able to transition to the design of complex digital logic systems.
Platform: | Size: 101376 | Author: 李茂国 | Hits:

[VHDL-FPGA-Verilog] myinterpolation

Description: 复杂的插值函数，用于颜色空间转换 verilog-The complex interpolation function for color space conversion verilog
Platform: | Size: 1024 | Author: zhangxinggang | Hits:

[Other] Verilog

Description: 《线逻辑的实现_复杂数字逻辑系统的Verilog》夏宇闻著，高清晰版经典教材-" Line of logic to achieve _ complex digital logic systems Verilog" Xia Yu smell, Gaoqingxiban classic textbook
Platform: | Size: 4646912 | Author: huluobo | Hits:

[Other] verilog

Description: 引入了Verilog HDL 硬件描述语言，向读者展示一种九十年代才真正开始在美国等先进的工业国家逐步推广的 数字逻辑系统的设计方法。借助于这种方法，在电路设计自动化仿真和综合工具的帮助下， 我们完全有能力设计并制造出有自己知识产权的DSP（数字信号处理）类和任何复杂的数 字逻辑集成电路芯片，为我国的电子工业和国防现代化作出应有的贡献。-The introduction of the Verilog HDL hardware description language, to show the reader a kind of nineties really began in the United States and other advanced industrial countries to gradually extend the digital logic system design. With this method, simulation and integrated circuit design automation tools help, we are fully capable to design and create their own intellectual property rights of DSP (digital signal processing) and any complex digital logic integrated circuit chip, for our electronic industry and make due contributions to national defense modernization.
Platform: | Size: 2217984 | Author: da liu | Hits:

[Documents] Verilog_shuzisheji

Description: 本章的目的是想通过对数字信号处理、计算（Computing）、算法和数据结构、编程语言和 程序、体系结构和硬线逻辑等基本概念的介绍，了解算法与硬线逻辑之间的关系从而引入 利用Verilog HDL 硬件描述语言设计复杂的数字逻辑系统的概念和方法。向读者展示一种 九十年代才真正开始在美国等先进的工业国家逐步推广的数字逻辑系统的设计方法-Purpose of this chapter is to through digital signal processing, computing (Computing), algorithms and data structures, programming languages and programs, the logical architecture and hard-line description of the basic concepts to understand the algorithm and the relationship between hard-line logical to introduce using hardware description language Verilog HDL design complex digital logic concepts and methods. Nineties to show the reader a kind of really started in the United States and other advanced industrial countries to gradually extend the number of logic system design
Platform: | Size: 22794240 | Author: 王双 | Hits:

[Documents] verilog

Description: verilog的各种编程实例 有源代码的从简单到复杂-verilog source code of various programming examples from the simple to the complex
Platform: | Size: 468992 | Author: 王双 | Hits:

[VHDL-FPGA-Verilog] 135classic_example_of_Verilog_design

Description: Verilog的135个经典设计实例，由简到繁，由浅入深，值得收藏！-Verilog' s 135 classic design example, from simple to complex, Deep and worth collecting!
Platform: | Size: 113664 | Author: 假如 | Hits:

[VHDL-FPGA-Verilog] cmultip

Description: 用VERILOG HDL 实现节省乘法器的16位复数乘法器-With VERILOG HDL achieve savings of 16-bit complex multiplier multiplier
Platform: | Size: 1024 | Author: xiaobai | Hits:

[VHDL-FPGA-Verilog] verilog-program

Description: 国外经典verilog程序集锦，含有从最简单的定时器创建到复杂逻辑的实现。-Classic Collection verilog program abroad, with the timer created from the most simple to complex logic.
Platform: | Size: 31744 | Author: 分析学习 | Hits:

[VHDL-FPGA-Verilog] 31705301sdram-control-verilog

Description: Summary: InterPreTS (Interaction Prediction through Tertiary Structure) is a web-based version of our method for predicting protein-protein interactions (Aloy and Russell, 2002, Proc. Natl Acad. Sci. USA, 99, 5896-5901). Given a pair of query sequences, we first search for homologues in a database of interacting domains (DBID) of known three-dimensional complex structures. Pairs of sequences homologous to a known interacting pair
Platform: | Size: 718848 | Author: wx | Hits:

[VHDL-FPGA-Verilog] 83399055ref-sdr-sdram-verilog

Description: Summary: InterPreTS (Interaction Prediction through Tertiary Structure) is a web-based version of our hod for predicting protein-protein interactions (Aloy and Russell, 2002, Proc. Natl Acad. Sci. USA, 99, 5896-5901). Given a pair of query sequences, we first search for homologues in a database of interacting domains (DBID) of known three-dimensional complex structures. Pairs of sequences homologous to a known interacting pair-Summary: InterPreTS (Interaction Prediction through Tertiary Structure) is a web-based version of our method for predicting protein-proteiinteractions (Aloy and Russell, 2002, Proc. Natl Acad. Sci. USA, 99, 5896-5901). Given a pair of query sequences, we first search for homologues in a database of interacting domains (DBID) of known three-dimensional complex structures. Pairs of sequences homologous to a known interacting pair
Platform: | Size: 718848 | Author: wx | Hits:

[VHDL-FPGA-Verilog] Verilog

Description: 针对Verilog语言，提供了135个经典的示例程序代码，从简单到复杂，一步步的深入。-For the Verilog language, providing 135 classic example code, from simple to complex, step by step in depth.
Platform: | Size: 113664 | Author: 杨春杰 | Hits:

[VHDL-FPGA-Verilog] 32_bit_complex_multiplier

Description: 一款32位复数乘法器，用verilog写的。-32_bit complex multiplier,written in verilog HDL.
Platform: | Size: 8192 | Author: wilson | Hits:
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