Search - convolutional 2 1 2

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[Communication] ViterbiAlg DL : 0: Viterbi译码,IS-95中的1/2码率的卷积码-Viterbi decoding, IS-95 of 1/2 the rate Convolutional Codes
Update : 2025-02-17 Size : 222kb Publisher : toshine
[matlab] conv_vit_qam DL : 0: Convolutional(2,1,6) Encoder and soft decision Viterbi Decoder
Update : 2025-02-17 Size : 1kb Publisher : huang
[matlab] conv_vit_qam DL : 0: Convolutional(2,1,6) Encoder and soft decision Viterbi Decoder 刚才上载的有错误,已修正-Convolutional (2,1,6) Encoder and soft decision Viterbi Decoder just uploaded a mistake, has been amended
Update : 2025-02-17 Size : 1kb Publisher : huang
[ELanguage] partab DL : 0: (2,1,9)卷积码的一个查找表,用与(2,1,9)卷积码的编码,可以根据寄存器的状态来判别输出数.-(2,1,9) convolutional code a lookup table, using and (2,1,9) convolutional code encoding may be based on the state register to determine the number of output.
Update : 2025-02-17 Size : 204kb Publisher : LIN
[DSP program] Viterbi DL : 0: （2,1,3）卷积码的Viterbi译码C程序，已经验证成功-(2,1,3) convolutional code C of the Viterbi decoding process, has proved to be successful
Update : 2025-02-17 Size : 1kb Publisher : dada
[Documents] QPSK DL : 0: 提出了一个采用(2,1,7)卷积码+QPSK的中频调制解调方案,并在Xilinx公司的100万门FPGA芯片上实现了该系统。该系统在信噪比SNR为6dB左右时可实现速率超过1Mbit/s、误码率小于10-5的数据传输。 -Proposed a use of (2,1,7) convolutional code+ QPSK modulation and demodulation of the IF program, and in Xilinx' s FPGA chip one million on implementation of the system. The system SNR to 6dB signal to noise ratio at about the rate may achieve more than 1Mbit/s, less than 10-5 bit error rate of data transmission.
Update : 2025-02-17 Size : 61kb Publisher : 张同星
[Windows Develop] CONVOLUTIONAL DL : 0: CONVOLUTIONAL encoder
Update : 2025-02-17 Size : 1kb Publisher : ali
[ELanguage] viterbi_decoder_for212 DL : 0: 本程序为（2，1，2）维特比译码程序，采用对BIT操作，译码速度特快，可扩展至(2,1,6)-viterbi decoder for(212) convolutional
Update : 2025-02-17 Size : 10kb Publisher : 刘斌
[VHDL-FPGA-Verilog] juanjima DL : 0: 卷积码的生成程序,为(2,1,3)移位寄存器的卷积码生成-Convolutional code generation process for the (2,1,3) convolutional code of the shift register to generate
Update : 2025-02-17 Size : 840kb Publisher : wind
[CSharp] simd-viterbi-2.0.1 DL : 0: 全面的维特比编码，m=7，data rate有1/2以及1/3两种，军实现通过-Viterbi decoding of rate-1/2 and rate-1/3 m=7 convolutional codes
Update : 2025-02-17 Size : 210kb Publisher : jiaqi yuan
[3G develop] 215test DL : 0: 用c语言实现(2,1,5)卷积码编码，viterbi解码。-With c language (2,1,5) convolutional code encoder, viterbi decoding.
Update : 2025-02-17 Size : 200kb Publisher : jasper
[VHDL-FPGA-Verilog] 123 DL : 0: 将通过仿真的VHDL 程序下载到FPGA 芯片EPF10K10LC84-3 上，取得了较为满意的结果。本设计选择的(3,1,2)卷积码和（2,1,1）卷积码,都是极具代表性的卷积码。因为卷积码具有相似的结构和特点，所以(3,1,2)卷积编码器和（2,1,1）卷积解码器的设计思想，具有普遍适用性。-Through the simulation of the VHDL program downloaded to the FPGA chip EPF10K10LC84-3, the obtained satisfactory results. The design choices (3,1,2) convolutional code and (2,1,1) convolutional code, are highly representative of convolutional codes. For convolutional codes with similar structure and characteristics, so (3,1,2) convolutional encoder and (2,1,1) convolutional decoder design has general applicability.
Update : 2025-02-17 Size : 5kb Publisher : 王彬
[Modem program] cc_encoder DL : 0: 卷积码编码C程序代码，码率为1/2,2/3等-Convolutional code encoder C code, rate 1/2, 2/3, etc.
Update : 2025-02-17 Size : 143kb Publisher : 于慕阳
[matlab] Hviterbi DL : 0: 实现卷积编码和相应的维特比译码（卷积码编码器为（2，1，3），维特比译码针对第1、3位模二加和第1、2位模二加）-Convolutional coding and the corresponding realization of Viterbi decoding (convolutional code encoder for the (2,1,3), Viterbi decoder bit mode for the first 1,3 and 1,2 position two plus two plus model )
Update : 2025-02-17 Size : 2kb Publisher : 张程
[Windows Develop] juanji DL : 0: 卷积编码，主要是（2,1,9）卷积编码器-Convolutional coding, mainly (2,1,9) convolutional encoder
Update : 2025-02-17 Size : 178kb Publisher : 魏玉晗
[Communication-Mobile] viterbi-3.0.1 DL : 0: Package viterbi-3.0.1.tar contains programs to implement Viterbi decoding of (de-facto standard) rate-1/2 and rate-1/3 m=7 convolutional codes. Package simd-viterbi-2.0.1.tar contains programs to implement Viterbi decoders for r=1/2 k=7 and k=9 codes that use the Intel/AMD SIMD instruction sets (MMX/SSE/SSE2).
Update : 2025-02-17 Size : 23kb Publisher : jiang core
[ELanguage] 213 DL : 0: （2，1，3）卷积码的编码和Veterbi译码，用C语言描述，可以跑通-（2,1,3） convolutional code encoding and decoding Veterbi, using C language description, you can run through
Update : 2025-02-17 Size : 229kb Publisher : bingle
[ELanguage] fec_convcode DL : 0: 卷积码的C语言代码实现，其中包括（2，1,2）卷积码编码器和维特比译码的实现。-Convolutional code C code implementation, including the (2,1,2) convolutional code encoder and Viterbi decoding.
Update : 2025-02-17 Size : 480kb Publisher : xiao2
[3G develop] CDMAturbo DL : 0: CDMA中的turbo码仿真,tuebo编码器的仿真很不错！-This script simulates the classical turbo encoding-decoding system. It simulates parallel concatenated convolutional codes. Two component rate 1/2 RSC (Recursive Systematic Convolutional) component encoders are assumed. First encoder is terminated with tails bits. (Info+ tail) bits are scrambled and passed to the second encoder, while second encoder is left open without tail bits of itself.
Update : 2025-02-17 Size : 19kb Publisher : 丁一
[CSharp] Viterbi_fulltrace DL : 0: (2,1,3)卷积码的编码及译码程序，封装成函数，无冗余子函数，简单易懂，运行时显示Viterbi译码全部过程-(2,1,3) convolutional code encoding and decoding process, encapsulated into a function, non-redundant Functions, easy to understand, run-time display the whole process of Viterbi decoding
Update : 2025-02-17 Size : 170kb Publisher : sijiaxi

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