Search - convolutional vhdl code

Search - convolutional vhdl code - List

[VHDL-FPGA-Verilog] conv_code DL : 0: 用VHDL实现卷积码编码，该码为（2.1.3）型卷积码。-using VHDL Convolutional coding, the code (2.1.3)- Convolutional Codes.
Update : 2025-02-17 Size : 1kb Publisher : 武汉
[Communication-Mobile] Viterbi DL : 0: 卷积码（2，1，6），完整的工程文件，已经调试通过-Convolutional code (2,1,6), complete engineering documents have been debugging through
Update : 2025-02-17 Size : 46kb Publisher : jishanyi
[Communication] viterbidecoder DL : 0: 2，1，7卷积码的viterbi译码算法的FPGA实现，内容详细，而且附带源代码。-2,1,7 convolutional code of viterbi decoding algorithm realize the FPGA and detailed, but the source code attached.
Update : 2025-02-17 Size : 1.59mb Publisher : Wayne
[VHDL-FPGA-Verilog] viterbi DL : 0: 卷积码编码及其Viterbi译码的实现-Convolutional code encoder and Viterbi decoding to achieve
Update : 2025-02-17 Size : 250kb Publisher : mediative
[Other] interleaver DL : 0: This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
Update : 2025-02-17 Size : 2kb Publisher : tomsontiger
[VHDL-FPGA-Verilog] viterbi DL : 0: verilog程序，实现了（2，1，4）卷积码编码，和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
Update : 2025-02-17 Size : 3kb Publisher : xiongherui
[Communication] conv.vhd DL : 0: 卷积编码的VHDL代码，公司内部资料，不是个人随便编写的-VHDL code of convolutional encoding
Update : 2025-02-17 Size : 6kb Publisher : 魏强
[VHDL-FPGA-Verilog] project DL : 0: convolutional encoder vhdl code, rate 1/2, k=3
Update : 2025-02-17 Size : 4kb Publisher : phani
[Software Engineering] generate_trellis_rsc_c DL : 0: vhdl code for convolutional encoder
Update : 2025-02-17 Size : 2kb Publisher : anjali
[ELanguage] job217 DL : 0: 实现（2，1，7）卷积编码以及相应的viterbi译码-(2,1,7) convolutional code and the corresponding Viterbi decoding
Update : 2025-02-17 Size : 1kb Publisher : 李响
[Other] viterbi213 DL : 0: 编码方式为213的Viterbi卷积码编码器和译码器的FPGA的实现，包含整个QuartusＩＩ的工程文件，解码方式为寄存器交换法-Encoding for the 213 convolutional code encoder and Viterbi decoder FPGA realization of the project file that contains the entire QuartusII, decoding method for the register exchange
Update : 2025-02-17 Size : 2.54mb Publisher : jenny
[Communication-Mobile] convencode2 DL : 0: 卷积码（2，1，3）编码过程。代码清晰简单，对应人民邮电版《通信原理》中卷积码编码过程-Convolutional code (2,1,3) encoder. Code is clear and straightforward, Telecommunications for the corresponding version of " Communication Principle" in the process of convolutional coding
Update : 2025-02-17 Size : 116kb Publisher : zhaodanlin
[VHDL-FPGA-Verilog] 123 DL : 0: 将通过仿真的VHDL 程序下载到FPGA 芯片EPF10K10LC84-3 上，取得了较为满意的结果。本设计选择的(3,1,2)卷积码和（2,1,1）卷积码,都是极具代表性的卷积码。因为卷积码具有相似的结构和特点，所以(3,1,2)卷积编码器和（2,1,1）卷积解码器的设计思想，具有普遍适用性。-Through the simulation of the VHDL program downloaded to the FPGA chip EPF10K10LC84-3, the obtained satisfactory results. The design choices (3,1,2) convolutional code and (2,1,1) convolutional code, are highly representative of convolutional codes. For convolutional codes with similar structure and characteristics, so (3,1,2) convolutional encoder and (2,1,1) convolutional decoder design has general applicability.
Update : 2025-02-17 Size : 5kb Publisher : 王彬
[VHDL-FPGA-Verilog] OFDM_FPGA DL : 0: OFDM的FPGA实现内含卷积编码交织，频偏检测完整的OFDM实现代码 -The FPGA contains OFDM convolutional coding to achieve interleaving, OFDM frequency offset detecting the full implementation code
Update : 2025-02-17 Size : 2.17mb Publisher : 何渊泽
[USB develop] vertibi DL : 0: (2,1,7)viterbi convolutional code encoding, decoding, debugging through, you can directly use
Update : 2025-02-17 Size : 3.54mb Publisher : tianzhu
[VHDL-FPGA-Verilog] convolution DL : 0: convolution卷积码生成器程序设计及仿真源代码-convolution convolutional code generator source code of program design and simulation
Update : 2025-02-17 Size : 149kb Publisher : ant
[VHDL-FPGA-Verilog] encoder DL : 0: 802.11a卷积码的实现，使用公式133和177，可以用标准viterbi解码-802.11a convolutional code to achieve, using the formula 133 and 177, you can use standard viterbi decoding
Update : 2025-02-17 Size : 1kb Publisher : Team
[VHDL-FPGA-Verilog] 15Turbo DL : 0: urbo码是1993年法国人Berrou提出的一种新型编码方法。它巧妙的将卷积码和随机交织器结合在一起；同时，采用软输出迭代译码来逼近最大似然译码-urbo code is 1993 French Berrou proposed a new encoding method. It is clever to convolutional codes and random interleaver together the same time, the use of soft-output iterative decoding to approximate the maximum likelihood decoding
Update : 2025-02-17 Size : 61kb Publisher : wangzhi
[Modem program] convolutional-encoder DL : 0: In this case is a convolutional encoding code for decoding the convolutional code, using VHDL language. This code provide the method of convolutional encoding for input data. (2,1,7)
Update : 2025-02-17 Size : 1kb Publisher : kimdaeyoung
[Program doc] Convolutional-encoder-VHDL-code-_-VHDL-Programmin DL : 0: convolutional encoder in vhdl
Update : 2025-02-17 Size : 327kb Publisher : sampath

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