Location:
Search - cpld 128
Search list
Description: vc++与vhdl代码,cpld接受pc串口指令,输出pwm信号控制伺服电机.双通道,各128级.使用了扩展ascii码
Platform: |
Size: 959427 |
Author: hxf |
Hits:
Description: 是128*64程序，也是现在用的最多的，是CPLD上面用的
Platform: |
Size: 46753 |
Author: 朱飞云 |
Hits:
Description: vc++与vhdl代码,cpld接受pc串口指令,输出pwm信号控制伺服电机.双通道,各128级.使用了扩展ascii码-vc++ with VHDL code, cpld accept pc serial commands, the output pwm signal to control servo motor. dual-channel, the 128. the use of extended ascii code
Platform: |
Size: 959488 |
Author: hxf |
Hits:
Description: 是128*64程序，也是现在用的最多的，是CPLD上面用的-128* 64 procedures, is now the most used is the CPLD used above
Platform: |
Size: 46080 |
Author: 朱飞云 |
Hits:
Description: 128位的地址译码器，在cpld或者fpga上实现兼可-128-bit address decoder, in the CPLD or FPGA implementation and may
Platform: |
Size: 1024 |
Author: 王石子 |
Hits:
Description: 使用Verilog HDL语言编写的驱动LCD12864的时序，可以直接用FPGA/CPLD驱动LCD12864了。-Using Verilog HDL language driver LCD12864 timing, can be directly used FPGA/CPLD driver LCD12864 the.
Platform: |
Size: 542720 |
Author: zhouming |
Hits:
Description: The MAX II CPLD has the following features:
■ Low-cost, low-power CPLD
■ Instant-on, non-volatile architecture
■ Standby current as low as 29 μA
■ Provides fast propagation delay and clock-to-output times
■ Provides four global clocks with two clocks available per logic array block (LAB)
■ UFM block up to 8 Kbits for non-volatile storage
■ MultiVolt core enabling external supply voltages to the device of either 3.3 V/2.5 V
or 1.8 V
■ MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels-The MAX® II family of instant-on, non-volatile CPLDs is based on a 0.18-μm, 6-layermetal-
flash process, with densities from 240 to 2,210 logic elements (LEs) (128 to 2,210
equivalent macrocells) and non-volatile storage of 8 Kbits. MAX II devices offer high
I/O counts, fast performance, and reliable fitting versus other CPLD architectures.
Featuring MultiVolt core, a user flash memory (UFM) block, and enhanced in-system
programmability (ISP), MAX II devices are designed to reduce cost and power while
providing programmable solutions for applications such as bus bridging, I/O
expansion, power-on reset (POR) and sequencing control, and device configuration
control.
Platform: |
Size: 612352 |
Author: 王广龙 |
Hits:
Description: The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection.
This design is targeted to the XCR3128XL-7VQ100C CoolRunner CPLD. This is a 3V, 128 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
-The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection.
This design is targeted to the XCR3128XL-7VQ100C CoolRunner CPLD. This is a 3V, 128 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
Platform: |
Size: 5120 |
Author: vijendra pal |
Hits:
Description: The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection.
This design is targeted to the XCR3128XL-7VQ100C CoolRunner CPLD. This is a 3V, 128 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
-The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection.
This design is targeted to the XCR3128XL-7VQ100C CoolRunner CPLD. This is a 3V, 128 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
Platform: |
Size: 6144 |
Author: vijendra pal |
Hits:
Description: 128位的地址译码器，在cpld或者fpga上实现兼可-128-bit address decoder, in the CPLD or FPGA implementation and may
Platform: |
Size: 1024 |
Author: wthat |
Hits: