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Description: CPLD下的A/D转换器TCL5510驱动源码-CPLD under the A / D converters TCL5510 driven FOSS
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Size: 35573 |
Author: 陈子牙 |
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Description: 周立功的USB大容量存储开发板带CPLD的代码D的源码-weeks meritorious USB Mass Storage Development strip CPLD the source code D.
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Size: 432780 |
Author: guoyaoming |
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Description: 错误检测与纠正电路的设计与实现用VHDL语言在CPLD上实现串行通信.doc-error detection and correction circuit design and implementation using VHDL on the CPLD serial communications. D oc
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Size: 213637 |
Author: 1 |
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Description: 本科教育的实体实例，其中包括3-8译码器，D触发器等逻辑模块，可以位初学CPLD的爱好者提供方便
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Size: 89015 |
Author: 小树 |
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Description: CPLD下的A/D转换器TCL5510驱动源码-CPLD under the A/D converters TCL5510 driven FOSS
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Size: 34816 |
Author: 陈子牙 |
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Description: 周立功的USB大容量存储开发板带CPLD的代码D的源码-weeks meritorious USB Mass Storage Development strip CPLD the source code D.
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Size: 432128 |
Author: guoyaoming |
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Description: 错误检测与纠正电路的设计与实现用VHDL语言在CPLD上实现串行通信.doc-error detection and correction circuit design and implementation using VHDL on the CPLD serial communications. D oc
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Size: 212992 |
Author: 1 |
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Description: 一个老外写的用CPLD实现DDS的软件，大家参考参考！-Written by a foreigner with CPLD realize DDS software, your information!
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Size: 4096 |
Author: 夕阳 |
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Description: CPLD-EPM7128SLC84最小系统及下载线，非常适合初学者入门学习。-CPLD-EPM7128SLC84 minimum system and download the line, very suitable for beginners learning portal.
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Size: 105472 |
Author: 威威 |
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Description: TI原产TMS320C6713DSK开发板中CPLD的内容源码，对自己做开发板非常具有参考价值
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Size: 31744 |
Author: 工 |
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Description: 用EPM7032（CPLD）做的２路８位并行输入ＤＡＣ，带内部环型振荡器（不用外接时钟振荡源）。-With EPM7032 (CPLD) to do 2-way 8-bit parallel input DAC, with the internal ring oscillator (no external clock oscillation source).
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Size: 3072 |
Author: 邵刚 |
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Description: AT89C51+CPLD 的EPM7064SLC44-10的学习板电路图-AT89C51+ CPLD
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Size: 644096 |
Author: 杨少栋 |
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Description: 本科教育的实体实例，其中包括3-8译码器，D触发器等逻辑模块，可以位初学CPLD的爱好者提供方便-Examples of undergraduate education entities, including the 3-8 decoder, D flip-flops and other logic modules, digital learning can facilitate fans CPLD
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Size: 89088 |
Author: 小树 |
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Description: 7段数码显示译码器设计7段数码是纯组合电路，通常的小规模专用IC，如74或4000系列的器件只能作十进制BCD码译码，然而数字系统中的数据处理和运算都是二进制的，所以输出表达都是十六进制的，为了满足十六进制数的译码显示，最方便的方法就是利用译码程序在FPGA/CPLD中来实现。例子作为七段译码器，输出信号LED7S的7位分别接数码管的7个段，高位在左，低位在右。例如当LED7S输出为“1101101”时，数码管的7个段g、f、e、d、c、b、a分别接1、1、0、1、1、0、1；接有高电平的段发亮，于是数码管显示“5”。-7 digital display decoder design 7 Digital is pure combinational circuits, usually of small-scale dedicated IC, such as 74 or 4000 Series devices can only be used to decimal BCD decoder, but digital systems in the data processing and computing are binary, so the output expression are hexadecimal, and hexadecimal number in order to meet the needs of the decoding shows that the most convenient way is to use decoding process in FPGA/CPLD in to achieve. Seven-Segment decoder as an example, the output signal of the seven were LED7S access digital pipe 7 above, high in the left, low in the right. For example, when LED7S output as
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Size: 82944 |
Author: lkiwood |
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Description: 基于C P L D 的伪随机序列发生器，用FPGA产生随机序列的-CPLD-based pseudo-random sequence generator, generate random sequences using FPGA
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Size: 248832 |
Author: jackk |
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Description: 2407A 内置 16 通道10 位AD 转换器，在 00IC2407＋CPLD 实验板上只扩展两通道，分
别是第0 通道和第8通道，DSP 能承受的A/D 输入信号是0－3.3V，在00IC2407+CPLD 实
验板上没有单独采用基准源，直接使用系统的3.3V作为A/D 转换器的基准信号。 -Built-2407A 16-channel 10-bit AD converter, in 00IC2407+ CPLD experiment board extended only two channels, namely, 0-channel and 8-channel, DSP can withstand the A/D input signal is 0-3.3V, in 00IC2407+ CPLD There is no separate test board with reference to directly use the system' s 3.3V, as A/D converter reference signal.
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Size: 79872 |
Author: lizhenli |
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Description: 基于CPLD的数据采集与监控系统设计.CPLD； 数据采集及监控； VHDL； A/D转换。-The design based on Data Acquisition and Monitoring System of CPLD
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Size: 214016 |
Author: 叶脉 |
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Description: 单片机-CPLD结构体系在电子设计中的相关应用-Microcontroller-CPLD structure of the system in the electronic design
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Size: 287744 |
Author: li |
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Description: FPGA/CPLD开发，基于VHDL语言的D触发器的实现-FPGA/CPLD development, based on VHDL implementation of the D flip-flop
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Size: 214016 |
Author: 刘志芳 |
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Description: The output frequency requirements for the three waveforms are: the frequency range is adjustable between 20Hz-20kHz; the phase difference between the three waveforms is 120 degrees.
A. of sine wave signal: step 10Hz; frequency stability: better than 1/10000; nonlinear distortion coefficient is less than 3%.
B. of the square wave signal is frequency: the rise and fall time of <1 s;
The requirements of C. for triangular wave signals are that the signal frequency range is adjustable between 20Hz-20kHz.
D. for the above three frequencies are required: the frequency can be preset; when the load is 600, the output signal amplitude is greater than 3V; the output signal amplitude can be adjusted in the range of 100mv~3V, the step length is 100mV.
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Size: 360448 |
Author: 东京的樱花飘过巴黎
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