Description: 智能全数字锁相环的设计用VHDL语言在CPLD上实现串行通信-DPLL intelligent design using VHDL on the CPLD Serial Communication Platform: |
Size: 793855 |
Author:1 |
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Description: 智能全数字锁相环的设计用VHDL语言在CPLD上实现串行通信-DPLL intelligent design using VHDL on the CPLD Serial Communication Platform: |
Size: 793600 |
Author:1 |
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Description: 文中给出了cPLD与单片机的串行通信的C语言代码与VHDL代码有一定的使用价值-In this paper, the CPLD and MCU serial communication C-language code and the VHDL code has certain value Platform: |
Size: 5120 |
Author:qibinchuan |
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Description: ＳＰＩ总线与ＣＰＬＤ之间的通信程序，可实现ＳＰＩ串行输入，通过移位寄存器后并行输出-SPI bus and the CPLD communication between these procedures is to realize SPI serial input, through the shift register parallel output after Platform: |
Size: 1024 |
Author:金臻炜 |
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Description: 采用CPLD实现串口通信（Verilog硬件描述语言）-Realize the use of CPLD serial communication (Verilog Hardware Description Language) Platform: |
Size: 5120 |
Author:wuzhidong |
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Description: 基于VHDL的异步串行通信电路设计 随着电子技术的发展，现场可编程门阵列FPGA和复杂可编程逻辑器件CPLD的出现，使得电子系统的设计者利用与器件相应的电子CAD软件，在实验室里就可以设计自己的专用集成电路ASIC器件。这种可编程ASIC不仅使设计的产品-VHDL-based asynchronous serial communication circuit design with the advent of electronic technology, field programmable gate array FPGA and CPLD Complex Programmable Logic Device emergence, the designers of electronic systems and devices using the corresponding electronic CAD software , in the laboratory can design their own application-specific integrated circuits ASIC devices. This not only makes the design of Programmable ASIC products Platform: |
Size: 1024 |
Author:chaiyiming |
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Description: -- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在
--PC机上安装一个串口调试工具来验证程序的功能。
-- 程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控
--制器，10个bit是1位起始位，8个数据位，1个结束
--位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实
--现相应的波特率。程序当前设定的div_par 的值是0x104，对应的波特率是
--9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间
--划分为8个时隙以使通信同步.
--程序的工作过程是：串口处于全双工工作状态，按动SW0，CPLD向PC发送“welcome"
--字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向CPLD发送0-F的十六进制
--数据，CPLD接受后显示在7段数码管上。-- The module s function is to verify the implementation and the basic PC-to serial communication functions. Required at
- PC machine on the installation of a serial debugging tools to verify the function of the procedure.
- Implementation of a program to send and receive a 10 bit (that is, no parity bit) Serial Control
- System, and 10 bit is a start bit, 8 data bits, 1 Ending
- Bit. Serial Porter law procedures defined by the parameters div_par decision to change the parameters can be real
- Is the corresponding baud rate. Procedures set div_par the current value is 0x104, the corresponding baud rate are
- 9600. 8 times the baud rate with a clock will be sent or received every bit of the cycle time
- Is divided into eight time slots in order to enable synchronous communication.
- Procedures for work processes are: full-duplex serial port in job status, rather than pressing SW0, CPLD to the PC to send "welcome"
- String (serial debug tools is set to accept by way of A Platform: |
Size: 65536 |
Author:johnson |
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Description: FPGA与CPLD之间通过串口通信的程序，波特率为9600。-FPGA and CPLD via the serial port communication program, the baud rate to 9600. Platform: |
Size: 285696 |
Author: |
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Description: 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。
程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。
串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值
是0x104，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通
信同步.
程序的基本工作过程是，按动一个按键SW0，控制器向PC的串口发送“welcome"，
PC机接收后显示验证数据是否正确（串口调试工具设成按ASCII码接受方式）.
PC可随时向CPLD发送0-F的十六进制数据，CPLD接受后显示在7段数码管上.-The module s function is to verify the implementation and the basic PC, the serial communication function. Need PC,
Install a serial debugging tools to verify the functionality of the program.
Program implements a receive a 10 bit (ie no parity bit) of the serial controllers, 10
bit is a start bit, 8 data bits, 1 stop bit.
Serial Porter law defined by the program parameters div_par decision can change the parameters of the corresponding
Baud rate. Program the value of the current set div_par
Is 0x104, the corresponding baud rate is 9600. 8 times the baud rate with a clock will be sent or received per
A bit of the cycle time is divided into eight time slots in order to pass
Information synchronization.
The basic process is the work program, press a button SW0, the controller s serial port to the PC
"Welcome",
PC, after receiving the authentication data displayed is correct (serial debugging tool ASCII code set by the r Platform: |
Size: 2048 |
Author:riversky |
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Description: CPLD+MCU电压采集系统
测试程序+原理图\测试程序\串行通信\收发-CPLD+ MCU voltage acquisition system
Schematic test procedure+ \ Test Programs \ serial communication \ transceivers Shuo Platform: |
Size: 1024 |
Author:cumtstone |
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Description: 一种利用CPLD实现波特率自动侦测的方法,介绍了数据接收模块系统,分析了波特率自动侦测原理,利用VHDL语言对其进行了编程,最后给出了仿真结果,从而推广该方法的应用。
关键词:串行通信,波特率,自动侦测,仿真结果
-CPLD realization of a use of automatic baud rate detection methodology, the data receiving module systems, analysis of the principle of auto-detect baud rate, using its programming language VHDL, the simulation results are given to the promotion of the application of the method. Keywords: serial communication, baud rate, automatic detection, simulation results Platform: |
Size: 128000 |
Author:枫蓝 |
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Description: 参加CPLD竞赛时的全部源码。内含DS18B20温度检测模块、串口通讯模块、GPRS手机拨号模块、6位密码锁模块、液晶LCD1602显示模块、播放音乐模块等等各种模块，相信大家一定用的着。-Participate in all the source code when CPLD contest. Containing DS18B20 temperature detection module, serial communication module, GPRS mobile phone dial-up module, six lock module, LCD LCD1602 display module, play music modules, and so a variety of modules, I believe we must use the. Platform: |
Size: 1728512 |
Author:王新锋 |
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Description: CPLD-based RS_232 serial communication to achieve基于CPLD的RS_232串口通信实现-CPLD-based RS_232 serial communication to achieve Platform: |
Size: 574464 |
Author:manapp |
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Search - cpld serial communication