Description: - The module s function is to verify the implementation and the basic PC-to serial communication functions. Required at
- PC machine on the installation of a serial debugging tools to verify the function of the procedure.
- Implementation of a program to send and receive a 10 bit (that is, no parity bit) Serial Control
- System, and 10 bit is a start bit, 8 data bits, 1 Ending
- Bit. Serial Porter law procedures defined by the parameters div_par decision to change the parameters can be real
- Is the corresponding baud rate. Procedures set div_par the current value is 0x104, the corresponding baud rate are
- 9600. 8 times the baud rate with a clock will be sent or received every bit of the cycle time
- Is divided into eight time slots in order to enable synchronous communication.
- Procedures for work processes are: full-duplex serial port in job status, rather than pressing SW0, CPLD to the PC to send "welcome"
- String (serial debug tools is set to accept by way of A
- [ uart from opencores] - VHDL implement serial port, it can commu
- [UART_16C554] - UART_16C554 design UART_16C554 Design
- [254646] - of dynamic digital scanning vhdl
- [PS2_RS232] - Realize PS/2 interface with RS-232 data
- [VHDL_UART] - VHDL language UART serial interface chip
- [COMJK] - Explain a computer serial port to contro
- [rs232] - dp_xiliux the CPLD Verilog design experi
- [music] - Design and debug a good one can produce
- [32ET_source] - 32 slot of the VHDL source code in the d
- [NIOSII-uartprogram] - SOPC technology use NIOS II serial Detai
File list (Check if you may need any files):
serial
......\Block1.bdf
......\serial.asm.rpt
......\serial.bdf
......\serial.bsf
......\serial.cdf
......\serial.done
......\serial.fit.eqn
......\serial.fit.rpt
......\serial.fit.smsg
......\serial.fit.summary
......\serial.flow.rpt
......\serial.map.eqn
......\serial.map.rpt
......\serial.map.summary
......\serial.pin
......\serial.pof
......\serial.qpf
......\serial.qsf
......\serial.qws
......\serial.sof
......\serial.tan.rpt
......\serial.tan.summary
......\serial_assignment_defaults.qdf
......\serial_test.bsf
......\serial_test.vhd
......\serial_test.vhd.bak
......\setup.tcl
......\setup.tcl.bak
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