Description: dp_xiliux the CPLD Verilog design experiments, serial presentation. code test.
- [verilogexample[43].Rar] - Embedded Programmable CPLD in a typical
- [Uart_TR] - Verilog prepared by the simple asynchron
- [rs232] - RS232 verilog design
- [UART] - Using FPGA to achieve the RS232 asynchro
- [xilinx_iic_spi] - IIC and xlinx official description of sp
- [uartverilog] - Via verilog language ,cpld can communcat
- [WIRELESS] - This file contains source code for DS-CD
- [rs232] - Full RS232 Verilog source code, support
- [RS232] - FPGA implementation of the RS232 serial
- [CPLD] - FPGA and CPLD via the serial port commun
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