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Description: 用指令预取反跟踪。CPU 的执行时并不是执行到哪一句再到内存中去取那一句，而是先读入到 CPU 的 Cache 中，如果指令已经到了 Cache 中，再将它修改也没有用了，如果用跟踪程序的话，CPU 的 Cache 中就不会是跟正常执行时的指令相同，所以可以改动下几条指令，当然是故意改错，如果没有跟踪，程序还回照常执行，有跟踪的话，那就...
-with instructions Prefetching anti-tracking. CPU implementation is not an execution where one memory then that a Mysteriously, but Dialer to the CPU cache, if the instructions had come to Cache, then amend it has not spent, if the tracking procedures, CPU cache is not on with the normal execution of the orders the same, it can alter the next several directions Of course deliberate error, in the absence of tracking procedures also open to the implementation, tracking, then the ...
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Size: 2060 |
Author: jiankang |
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Description: 一个利用DLL实现获得CPU信息的代码，十分专业，不但可以获得CPU的速度、型号等，而且可以获得CPU的缓存大小、流水线数等等30多项CPU的特性，而且，带了DLL的VC源程序-a DLL using information obtained CPU code, very professional, not only can the CPU speed, models, but the available CPU cache size, number, etc. Line 30 of the characteristics of the CPU, but with a VC source DLL
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Size: 96502 |
Author: 王远勤 |
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Description: 用于计算机系统结构中多CPU Cache一致性写协议的演示，MFC
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Size: 54543 |
Author: superace |
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Description: 主控程序，协调内存，cpu直间缓存操作-control procedures, coordination of memory, cpu cache operation between straight
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Size: 1025 |
Author: 李翔 |
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Description: 一个利用DLL实现获得CPU信息的代码，十分专业，不但可以获得CPU的速度、型号等，而且可以获得CPU的缓存大小、流水线数等等30多项CPU的特性，而且，带了DLL的VC源程序-a DLL using information obtained CPU code, very professional, not only can the CPU speed, models, but the available CPU cache size, number, etc. Line 30 of the characteristics of the CPU, but with a VC source DLL
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Size: 96256 |
Author: 王远勤 |
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Description: 主控程序，协调内存，cpu直间缓存操作-control procedures, coordination of memory, cpu cache operation between straight
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Size: 1024 |
Author: 李翔 |
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Description: 这个代码使用了几个类,即可获取计算机中CPU的信息,包括CPU频率,型号,生产商,二级缓存,CPU技术特征,所有寄存器位置等.没有使用微软的WMI库编程-the code used several categories, the computer can access the CPU information, including CPU frequency, type, manufacturer, two cache, CPU technical features, register all locations. Do not use Microsoft's WMI programming library
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Size: 37888 |
Author: 大头文 |
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Description: 显示CPU信息的程序，能显示当前CPU频率，缓存等一系列信息-CPU information indicates the procedures that can show the current CPU frequency, a series of cache information
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Size: 25600 |
Author: 李树永 |
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Description: 精简CPU设计，需要的可以下来看看,是VERILOG语言写的-streamlined CPU design, the need to be down look at the language is written in verilog
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Size: 79872 |
Author: 磊 |
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Description: 用于计算机系统结构中多CPU Cache一致性写协议的演示，MFC-Computer system architecture for multi-CPU Cache Consistency demonstration written agreement, MFC
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Size: 54272 |
Author: superace |
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Description: 一个很有名的硬件模拟器。可以模拟CPU，cache，以及内存等。支持多核处理器的模拟。-A well-known hardware simulator. Can simulate the CPU, cache, and memory. Support multi-core processor simulation.
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Size: 4423680 |
Author: 雷田 |
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Description: MIPS CPU tested in Icarus Verilog
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Size: 20480 |
Author: imromeo |
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Description: cpu设计实例mips。MIPSI指令集32位CPU （1）MiniCore设计实例全32位操作，32个32位通用寄存器，所有指令和地址全为32位
（2）静态流水线（3～5级）
（3）Forwarding技术
（4）片内L1 Cache，指令、数据各4KByte，硬件初始化
（5）没有TLB，但系统控制协处理器（CP0）具有除页面映射外的全部功能
-cpu design example mips. MIPSI instruction set 32-bit CPU
(1) MiniCore design example of the entire 32-bit operation, 32 32-bit general-purpose registers, all the commands and addresses are all 32-bit (2) static line (3 ~ 5)
(3) Forwarding technology (4 )-chip L1 Cache, command, data of all 4KByte, hardware initialization
(5) there is no TLB, but the system control coprocessor (CP0) with the exception of pages outside the full functionality of mapping
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Size: 27648 |
Author: 游笑 |
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Description: 简单5级流水线CPU的verilog逻辑设计-Simple line 5 of the CPU logic design verilog
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Size: 1024 |
Author: 张健 |
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Description: 开源的基于SystemC的模拟器，可以模拟ARM CPU, Cache, DDR，NOR, NAND, 时序和功耗均可以正确模拟。-This simulator is a cycle-accurate system-level energy and timing simulator. Developed by Embedded Low-Power Laboratory, Seoul National University. The simulator’s underlying kernel is OSCI SystemC 2.2.0. All of the hardware modules satisfies the OSCI standards.
The simulator is composed of a CPU, cache, and memory components including DDR SDRAM, MLC NOR Flash, MLC NAND Flash, SRAM. Each memory components have it’s own memory model, which enables cycle-accurate power consumption estimation of the devices. Master and slave SystemC IPs are connected through AMBA AHB CLI (Cycle-Level Interface). You will get energy trace files for each memory devices. You will get cycle-accurate performance evaluation results CPU cycle counts information, and cache hit/miss ratio on console. Also, you can get trace files for memory devices.
The simulator exhibits performance over 500 K instructions/sec, which is fairly high for a cycle-accurate system-level simulator.
The simulator’s source co
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Size: 4886528 |
Author: Archie |
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Description: 用Verilog实现一个简单的流水线CPU，并运行一个Quicksort程序。这是Berkley，eecs系的计算机系统结构课程实验的实验三。-This file is written in Verilog to achieve a simple pipeline CPU, which can run a Quicksort program.
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Size: 28672 |
Author: Matgek |
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Description: 缓存基础，对各种缓存的介绍，包括浏览器缓存，cpu缓存，内存缓存，磁盘缓存等。-Cache based on the introduction of various caches, including browser cache, cpu cache, memory cache, disk caching.
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Size: 764928 |
Author: zzq |
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Description: MN10300 CPU cache invalidation routines, using automatic purge registers.
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Size: 1024 |
Author: fxfisq |
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Description: MN10300 CPU cache invalidation routines.
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Size: 9216 |
Author: kaivongwou |
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Description: 当时的课程设计，16位多级无cache流水cpu的源码(Curriculum design at that time, 16 multi-level non cache flow CPU source code)
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Size: 2952192 |
Author: 祭绛烟
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