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[VHDL-FPGA-Verilog] cpuTerminate

Description: 用VHDL 编写的一个16位的cpu 设计方案，可以执行8条指令。-use VHDL to prepare a 16 cpu design of the program, the implementation of eight instructions.
Platform: | Size: 2108416 | Author: 宋文强 | Hits:

[VHDL-FPGA-Verilog] the-design-of-16-bit-cpu

Description: 用vhdl硬件语言设计的16位cpu，上传的压缩包既包含源代码又包含详细的文档说明。-with vhdl hardware design language of the 16 cpu, Upload compressed contains both the source code also contains a detailed document shows.
Platform: | Size: 128000 | Author: 晶晶 | Hits:

[Embeded-SCM Develop] demo9_CPU32

Description: 基于fpga和sopc的用VHDL语言编写的EDA的32位Nios CPU嵌入式系统软硬件设计-FPGA and SOPC based on the use of VHDL language EDA 32-bit Nios CPU embedded system software and hardware design
Platform: | Size: 926720 | Author: 多幅撒 | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 简单的16位CPU的VHDL设计 vhdl代码和cpu设计过程-Simple 16-bit CPU design of the VHDL code and VHDL design process cpu
Platform: | Size: 1488896 | Author: kilva | Hits:

[VHDL-FPGA-Verilog] MyCPU16

Description: 16位cpu设计VHDL源码，其中包括alu，clock，memory等部分的设计-16 cpu design VHDL source code, including alu, clock, memory and other parts of the design
Platform: | Size: 1089536 | Author: 孙冰 | Hits:

[VHDL-FPGA-Verilog] RiscCPU8

Description: 可综合的VerilogHDL设计实例: ---简化的RISC 8位CPU设计简介--- -VerilogHDL be integrated design example:--- simplified RISC 8 bit CPU design Introduction---
Platform: | Size: 219136 | Author: hulin | Hits:

[Com Port] serialrxtx

Description: 个人原创，已经测试通过。功能：完成串行数据与RS232格式数据的收发转换，ST16C450+串并双向转换兼收发时序产生功能，优点：省去了传统的ST16C450需要CPU干预的缺点，简化设计， 纯硬件自动转换，缺点：忽略各种异常报警，适用于误码测试时使用（传输错误由误码测试功能模块完成检测）。-Personal originality, have the test. Function: the completion of serial data and send and receive RS232 data format conversion, ST16C450+ String and two-way conversions and transceivers generate timing features, advantages: eliminating the traditional need for CPU intervention ST16C450 shortcomings, simplify the design, pure hardware automatically converted, disadvantages: ignore the various abnormal alarm, error test applies to the use of (transmission errors by the error detection test function modules completed).
Platform: | Size: 26624 | Author: fg0112 | Hits:

[VHDL-FPGA-Verilog] Chapter10

Description: 第十章的代码。 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示-Chapter X code. This book by more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of additions device/counters, multipliers/dividers, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and the results demonstrate
Platform: | Size: 6872064 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] cpu_16bit

Description: design cpu 16 bits by verilog HDL.
Platform: | Size: 1024 | Author: tommy | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 用VHDL编的简易16位和8位CPU，可完成加减乘法移位等功能，拥有源码和设计文档，资料齐全-Compiled with VHDL simple 16-bit and 8-bit CPU, to be completed by addition and subtraction multiplication shift functions, with source code and design documents, data and complete
Platform: | Size: 1489920 | Author: 雄鹰 | Hits:

[VHDL-FPGA-Verilog] PIPE_LINING_CPU_TEAM_24

Description: 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,rs,rt slti rt,rs,imm sltiu rt,rs,imm sllv rd,rt,rs sra rd,rt,shamt blez rs,imm j target lwl rt,offset(base) lwl rt,offset(base) lw rt,imm(rs) sw rt,imm(rs) 在本设计中，采取非常良好的模块化编程风格，共分十三个主要模块PIPE_LINING_CPU_TEAM_24.v为顶层实体文件，对应为PIPE_LINING_CPU_TEAM_24模块作为顶层实体模块，如下： ifetch.v、regdec.v、exec.v、mem.v、wr.v分别实现五个流水段； cpuctr.v用于产生CPU控制信号； ALU.v用于对操作数进行相应指令的运算并输出结果； DM.v数据存储器 IM.v指令存储器 datareg.v数据寄存器堆 extender.v位扩展 yiwei_32bits.v 实现32位四种移位方式的移位器 在顶层实体中，调用ifetch.v、regdec.v、exec.v、mem.v、wr.v这五个模块就实现了流水线CPU。顶层模块的结构清晰明了。对于学习verilog编程非常有用- Quatus II compiled by the environment, using Verilog HDL language to achieve a five-stage pipeline CPU. To complete the following 22 commands (not considering the virtual address and Cache, and the default mode for the small end): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo rd, rs clz rd, rs slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwl rt, offset (base) lw rt, imm (rs) sw rt, imm (rs) In this design, take a very good modular programming style, is divided into 13 main modules PIPE_LINING_CPU_TEAM_24.v for the top-level entity file, the corresponding module as a top-level entity for the PIPE_LINING_CPU_TEAM_24 modules, as follows: ifetch.v, regdec.v, exec.v, mem.v, wr.v water were to achieve the five paragraph cpuctr.v used to generate CPU control signal ALU.v accordingly
Platform: | Size: 4946944 | Author: 石 | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 用VHDL设计的cpu 用微指令方法设计 通过rom查表的方式进行设计-Cpu design with VHDL designed by microinstructions way through the design of look-up table rom
Platform: | Size: 1482752 | Author: 束佳云 | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 一个简单的CPU设计，支持add，sub，mvi，mv四条指令，用Verilog语言编写，在Quratus II上编译通过，仿真正确。-A simple CPU design, support add, sub, mvi, mv four instructions, with the Verilog language, compiled by the Quratus II, the simulation is correct.
Platform: | Size: 931840 | Author: 姜涛 | Hits:

[VHDL-FPGA-Verilog] cpu-design

Description: 采用VHDL实现的CPU设计代码，工程中包含测试波形。包含CPU设计文档，如指令格式设计和各功能模块说明和指令测试序列，能下载到实验台上直接运行。-CPU design is realized by VHDL Language, the project contains the test waveform. Contains the CPU design documents, such as directives format, instructions for each function module and test sequence. The project can run directly downloaded to the experiment.
Platform: | Size: 1600512 | Author: yuuuuuu | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 基于VHDL的简易CPU设计，可以实现加、减、乘三种运算，模拟CPU的运算过程通过指令实现运算-Simple CPU design based on VHDL, three operation can realize add, subtract, multiply, simulation of the CPU operation process operation was achieved by instruction
Platform: | Size: 1117184 | Author: llx | Hits:

[Software Engineering] CPU

Description: 我是2014级复旦的研究生。这是一个8位的CPU设计VHDL实现。本CPU基于RISC架构，实现了cpu的基本功能如：加减乘除运算，跳转等。此外，里面有一个17位的ROM区，是存储指令的。你可以写出一段17位的指令代码，并放入ROM区，该CPU即可自动运行出结果。压缩包里是源代码和我们当时的设计要求。本源代码的最后调试时在地址0 17是放入的斐波纳契数字(Fibonacci Numbers)指令。通过modelsim仿真即可看到结果。-I am a 2014 graduate of Fudan University. This is an 8-bit CPU design VHDL implementation. The CPU based on RISC architecture to achieve the basic functions, such as cpu: arithmetic operations, jumps and so on. In addition, there are a ROM area 17, is stored in the instruction. You can write some 17 of the instruction code, and placed in the ROM area, the CPU will automatically run the result. Compression bag is the source code and design requirements of our time. When the final commissioning source code is placed in the address 0 17 of Fibonacci numbers (Fibonacci Numbers) instruction. You can see the results of the simulation by modelsim.
Platform: | Size: 520192 | Author: ljt | Hits:

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