Search - crc cyclic redundancy check using VHDL

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[VHDL-FPGA-Verilog] CRC-Verilog DL : 0: 此是进行循环冗余效验的Verilog编码，适合多种标准，如CRC16-this Cyclic Redundancy is well-tested Verilog code for a variety of criteria, such as CYXLIC REDUNDANCY
Update : 2025-02-17 Size : 3kb Publisher : 藏瑞
[VHDL-FPGA-Verilog] CRC DL : 0: 利用VHDL语言,用FPGA设计一个数据通信中常用的数据检错模块—循环冗余校验CRC模块,选用当前应用最广泛的EDA软件QUARTUS II作为开发平台-Using VHDL, FPGA design of a common data in data communication error detection module- Cyclic Redundancy Check (CRC) module, currently the most widely used EDA software QUARTUS II as a development platform
Update : 2025-02-17 Size : 2kb Publisher : liangqing
[VHDL-FPGA-Verilog] CRC DL : 0: 赛灵思的循环冗余校验（CRC），内服详细说明-The Cyclic Redundancy Check (CRC) is a checksum technique for testing data reliability and correctness. This application note shows how to implement Configurable CRC Modules with LocalLink interfaces. Users tailor the module features to suit the protocol or application implemented in their system. The user-specified options for each of the configurable features are input parameters to the VHDL code for the modules. The VHDL source files for the CRC modules are coded using generate statements. The modules have two LocalLink interfaces: an upstream interface (US) and a downstream interface (DS)
Update : 2025-02-17 Size : 206kb Publisher : 我是谁