Search - cy7c68013 Verilog

Search - cy7c68013 Verilog - List

[Other resource] 68013FIFOIN DL : 0: Verilog HDL 编写的CY7C68013 SLAVE FIFO接口程序，实际测试可用。可以直接跟上位机连接，传输数据。
Update : 2008-10-13 Size : 649.62kb Publisher : huanghui
[SourceCode] CY7C68013读写FIFO源代码 DL : 0: CY7C68013读写FIFO源代码（Verilog）,已测试
Update : 2010-12-30 Size : 4.75kb Publisher : ranyq1143
[VHDL-FPGA-Verilog] CY7c68013_fpga_write_sram DL : 0: FPGA将从CY7C68013读到的数写入SRAM-FPGA will read a few CY7C68013 write SRAM
Update : 2025-02-17 Size : 280kb Publisher : 简
[Other Embeded program] USB2.0_Slave_FIFO_ASync DL : 0: This an USB2.0 chip CY7C68013 Configuraion Example for Slave FIFO mode with "async" mode.
Update : 2025-02-17 Size : 121kb Publisher : MyName
[VHDL-FPGA-Verilog] 68013FIFOIN DL : 0: Verilog HDL 编写的CY7C68013 SLAVE FIFO接口程序，实际测试可用。可以直接跟上位机连接，传输数据。-Verilog HDL prepared CY7C68013 SLAVE FIFO interface program, the actual test can be used. Keep pace with the digital machine can be directly connected to transmit data.
Update : 2025-02-17 Size : 649kb Publisher : huanghui
[VHDL-FPGA-Verilog] T2_USB_IN DL : 0: usb芯片cy7c68013从fpga中读入数据的演示程序，verilog语言-CY7C68013 chip usb read from the FPGA into the data presentation process, verilog language
Update : 2025-02-17 Size : 241kb Publisher : ones
[SCM] USB_kz DL : 0: 提供Cy7C68013 USB芯片开发源程序，由verilog编写-Cy7C68013 USB chip to provide the development of source code, prepared by the Verilog
Update : 2025-02-17 Size : 1kb Publisher : sky
[Applications] Asynchronous_slavefifo_wr DL : 0: usb-cy7c68013异步写传输代码verilog-usb-cy7c68013 asynchronous transfer write verilog code
Update : 2025-02-17 Size : 2kb Publisher : 罗玉明
[Program doc] 68013_SlaveFIFO DL : 0: cy7c68013工作在SLAVE FIFO下的FPGA源代码，已经通过，Verilog编写-cy7c68013 slave fifo mode code ,written by hard ware language
Update : 2025-02-17 Size : 2.05mb Publisher : 杨瑞
[Other] 68013 DL : 0: 介绍了此控制器与FPGA接口的控制和HDL (硬件描述语言)实现方法。利用CY7C68013控制器的 Slave F IFO从机方式,用Verilog HDL在FPGA中产生相应的控制信号,实现对数据的快速读写。试验结果表明此方案传输速度快、数据准确,可扩展到其他需要通过USB进行快速数据传输的系统中-This paper describes the controller and the FPGA interface to control and HDL (hardware description language) implementations. Use CY7C68013 controller Slave F IFO slave mode, using Verilog HDL in the FPGA generate a corresponding control signal to achieve fast read and write data. The results show that this program transmission speed, accurate data can be expanded to other needs through the USB for fast data transfer system
Update : 2025-02-17 Size : 357kb Publisher : 余岳衡
[VHDL-FPGA-Verilog] CY7C68013 DL : 0: USB2.0的Verilog实现，含有完整的FPGA代码-Use Verilog to implement the USB2.0 protcol
Update : 2025-02-17 Size : 586kb Publisher : XCP
[USB develop] usbFPGAconnect DL : 0: 该例程是PC机通过FX2-CY7C68013-A的USB2.0控制芯片与FPGA实现通信。其中的工程和代码包括PC机上的USB固件程序、驱动程序、上位机程序，FPGA上的VERILOG通信程序。-The routine is a PC, through the FX2-CY7C68013-A of the USB2.0 controller chip and the FPGA to achieve communication. One of the projects and code, including PC, the USB firmware, drivers, FPGA' s Communication Program
Update : 2025-02-17 Size : 6.82mb Publisher : 梁先国
[VHDL-FPGA-Verilog] Verilog_CY7C68013-SLAVE-FIFO DL : 0: 用VERILOG 编写 CY7C68013 usb数据采集SLAVE FIFO模式驱动程序，已验证过-Prepared with the VERILOG CY7C68013 usb data acquisition SLAVE FIFO mode driver, has proven
Update : 2025-02-17 Size : 652kb Publisher : 高亮
[VHDL-FPGA-Verilog] cy7c68013fpga_code DL : 0: cy7c68013的fpga配置代码，verilog语法-cy7c68013 the fpga configuration code, verilog syntax
Update : 2025-02-17 Size : 369kb Publisher : dingxing
[VHDL-FPGA-Verilog] FPGA-port_Verilog_HDL DL : 0: CY7C68013与FPGA接口的Verilog HDL实现，经过本人实验检验过的，-CY7C68013 and FPGA interface Verilog HDL realize the experiment after I test
Update : 2025-02-17 Size : 180kb Publisher : chenkun
[Driver Develop] USBSAMPLE DL : 0: 使用VERILOG语言编写的CY7C68013与FPGA程序，FPGA采用ALTREA公司-Use VERILOG language program CY7C68013 and FPGA, FPGA using ALTREA company
Update : 2025-02-17 Size : 4.81mb Publisher : comeboy6666
[VHDL-FPGA-Verilog] 13_usb_test DL : 0: fpga usb2.0 cy7c68013 黑金的板子(fpga usb2.0 cy7c68013)
Update : 2025-02-17 Size : 597kb Publisher : 翻山越岭
[VHDL-FPGA-Verilog] CY7C68013固件程序 FPGA测试Verilog程序 DL : 0: CY7C68013固件程序 FPGA测试Verilog程序(CY7C68013 firmware, FPGA test, Verilog)
Update : 2025-02-17 Size : 194kb Publisher : regan_wang
[VHDL-FPGA-Verilog] ezusb_io_latest.tar DL : 0: CY7C68013实现FPGA控制的USB接口通信，已通过测试(CY7C68013 FPGA control to achieve the USB interface communication, has passed the test)
Update : 2025-02-17 Size : 3kb Publisher : regan_wang
[Other] CY7C68013 Verilog test DL : 0: CY7C68013固件程序以及 FPGA测试Verilog程序，源代码(CY7C68013 firmware program FPGA test Verilog program, source code)
Update : 2025-02-17 Size : 194kb Publisher : 任小刀

« 12 »