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Description: 分频器的设计，包含普通分频器和占空比为50 的奇数分频 ；4位乘法器的VHDL程序；-Crossover design, including general divider and the duty cycle of 50 of the odd frequency 4-bit multiplier VHDL procedures
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Size: 8192 |
Author: 倪明 |
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Description: 使用VHDL进行分频器设计
本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设
计，包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数
（N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可
通过Synplify Pro或FPGA生产厂商的综合器进行综合，形成可使
用的电路，并在ModelSim上进行验证。-For crossover design using VHDL
This paper describes the use of examples in the FPGA/CPLD design using VHDL for divider
Design, including even frequency, duty cycle and 50 of non-50 duty cycle of the odd frequency, half-integer
(N+0.5) frequency, fractional, fractional and integral crossover frequency. Can all achieve
Synplify Pro FPGA by or integrated device manufacturers an integrated, enables the formation of
With the circuit, and on the ModelSim verification.
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Size: 322560 |
Author: guoguo |
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Description: 任意整数分频器，通过改变参数，可设置所需要的分频频率和占空比-Arbitrary integer divider, by changing the parameters, you can set the desired crossover frequency and duty cycle
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Size: 22528 |
Author: ifeng |
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Description: 本文使用实例描述了在 FPGA/CPLD 上使用 Verilog进行分频器设计，主要包括50 占空比的奇数分频.
-This article uses the example describes the crossover design using Verilog in FPGA/CPLD, including the 50 duty cycle odd divider
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Size: 273408 |
Author: 唐阳 |
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Description: 本例程为简易分频器。 实验前，请用排线（杜邦线）将TX-1C学习板的P1^0管脚与P3^2(INT0)管脚相连。因为P1^0用来模拟外界波形输入，它提供周期为100ms的方波，与T1管脚相连后，T1可对其进行周期计数。 程序中的变量pp决定着分频系数，其值乘以2即为分频系数。 改变其值可以得到相应的分频输出波形（方波）。P1^1为输出管脚，将其连接示波器可以看到分频后的波形。-This routine for simple frequency divider. Before experiment, please use platoon line (dupont line) will TX- 1 c ^ 0 learning plate P1 of the pin and P3 ^ 2 (INT0) pin connected. Because P1 ^ 0 used to simulate the outside world wave input, it provides cycle for 100 ms square wave, and T1 pin connected, T1 can carry on the cycle count. The procedure in the variable pp determines the scale coefficient, the value multiplied by 2 is the crossover factor. To change its value can get corresponding crossover output waveform (square). P1 ^ 1 as output pin, its connection oscillograph can see points after the frequency of the wave.
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Size: 22528 |
Author: zhanghuasheng |
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Description: VHDL分频器设计，本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设计，包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数（N+0.5）分频、小数分频、分数分频以及积分分频。-VHDL divider design, this article describes use cases, including even divide, non-50 duty cycle and 50 duty cycle odd divider, half integer (N+0-crossover design using VHDL for FPGA/CPLD .5) divider, fractional, fractional divider and integral divider.
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Size: 320512 |
Author: 黄玲 |
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Description: 本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设计，包括偶数分频、非 50 占空比和50 占空比的奇数分频、半整数（N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合，形成可使用的电路，并在 ModelSim 上进行验证。-This paper describes the use of examples prescaler to use VHDL design on FPGA/CPLD, including even frequency, non-50 duty cycle and 50 duty cycle odd frequency, half-integer (N+0.5) Divide, fractional, fractional and integral crossover frequency. All can be achieved through Synplify Pro FPGA synthesizer manufacturer or integrated to form a circuit that can be used and verified in ModelSim.
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Size: 339968 |
Author: liufei |
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Description: 这是我自己的一个流水灯的设计编程 在ise10.1环境下做的Verilog编程 用Spartan3E basys2开发板可以实现八个led灯的循环 有一个复位rst
设计关键是分频器的设计 这里运用的是d触发器实现50MHz的50M分频-This is my own design of a light water program in ise10.1 do Verilog programming environment with Spartan3E basys2 development board can achieve eight led lights rst design cycle has a reset key is to use a crossover design is here d trigger realization of 50MHz 50M Divide
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Size: 380928 |
Author: 赵龙 |
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