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Description: 用DA转换＋比较器的方法对外界模拟信号进行检测，同时这种联合装置加上CPLD可以代替低频AD转换器的功能-+ DA converters used for the comparison to the outside world analogue signal detection, at the same time with the Joint CPLD device can replace low-frequency AD converter functions
Platform: |
Size: 1918 |
Author: 赵天 |
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Description: CPLD源码 达芬奇开发套件 很好 <没找到!>
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搜索因特网-CPLD source da Vinci Boards good
Platform: |
Size: 223959 |
Author: baiyanru |
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Description: 本实验用DA转换＋比较器的方法对外界模拟信号进行检测，同时这种联合装置加上CPLD可以代替低频AD转换器的功能。-this experiment + DA conversion method of comparison to the outside world analog signal detection, while such joint CPLD devices can be replaced with low-frequency AD converter functions.
Platform: |
Size: 9434 |
Author: cheng |
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Description: ad取样，经由cpld处理，存入ram 1000点并由串行的da进行还原
Platform: |
Size: 180893 |
Author: 大星 |
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Description: 用DA转换＋比较器的方法对外界模拟信号进行检测，同时这种联合装置加上CPLD可以代替低频AD转换器的功能-+ DA converters used for the comparison to the outside world analogue signal detection, at the same time with the Joint CPLD device can replace low-frequency AD converter functions
Platform: |
Size: 2048 |
Author: 赵天 |
Hits:
Description: CPLD源码 达芬奇开发套件 很好 <没找到!>
查询更多词典
搜索因特网-CPLD source da Vinci Boards good
Platform: |
Size: 223232 |
Author: baiyanru |
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Description: 本实验用DA转换＋比较器的方法对外界模拟信号进行检测，同时这种联合装置加上CPLD可以代替低频AD转换器的功能。-this experiment+ DA conversion method of comparison to the outside world analog signal detection, while such joint CPLD devices can be replaced with low-frequency AD converter functions.
Platform: |
Size: 9216 |
Author: cheng |
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Description: 2812 DA，定时器中断1，2，3，外部中断-2812 DA, the timer interrupt 1,2,3, external interrupt
Platform: |
Size: 154624 |
Author: 戴杰 |
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Description: TMS320F28335开发例程,包括USB,串口,AD,DA-TMS320F28335 development of routines, including USB, serial, AD, DA
Platform: |
Size: 5382144 |
Author: |
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Description: ad取样，经由cpld处理，存入ram 1000点并由串行的da进行还原-ad sampling, by the CPLD deal, deposited by the serial ram 1000 points to restore the da
Platform: |
Size: 180224 |
Author: |
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Description: 步进电机8细分CPLD相序及外部DA输出
实际细分数可达64细分
使用Atmel maxplus2 V10.1软件-8 breakdown CPLD stepper motor phase sequence and external output of the actual breakdown of the number of DA up to 64 segments using Atmel maxplus2 V10.1 software
Platform: |
Size: 287744 |
Author: 陈国建 |
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Description: 使用FPGA/CPLD设置语音AD、DA转换芯片AIC23，FPGA/CPLD系统时钟为24.576MHz
1、AIC系统时钟为12.288MHz，SPI时钟为6.144MHz
2、AIC处于主控模式
3、input bit length 16bit output bit length 16bit MSB first
4、帧同步在96KHz-The use of FPGA/CPLD set voice AD, DA conversion chip AIC23, FPGA/CPLD system clock for the 24.576MHz 1, AIC system clock is 12.288MHz, SPI clock is 6.144MHz 2, AIC is in master mode 3, input bit length 16bit output bit length 16bit MSB first 4, frame synchronization at 96KHz
Platform: |
Size: 2048 |
Author: 张键 |
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Description: APPCM算法和AD/DA芯片驱动在CPLD中的实现，已在实际硬件中测试OK，quartus2环境-APPCM algorithm and AD/DA chip in the drive to achieve in the CPLD has been tested in actual hardware OK, quartus2 environment
Platform: |
Size: 1327104 |
Author: jiajunxian |
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Description: 达芬奇系统 TMS320DM6446 CPLD-GMMA 原理图 -Leonardo da Vinci system TMS320DM6446 CPLD-GMMA schematic diagram
Platform: |
Size: 223232 |
Author: DsForM |
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Description: 输入频率,用CPLD驱动8位DA,产生正玄信号-用CPLD驱动8位DA,产生正玄信号
Platform: |
Size: 1024 |
Author: 鲁先生 |
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Description: 51单片机+CPLD结构，小板上集成了发光二极管，蜂鸣器，数码管，红外接收头，继电器，实时时钟，按键，AD（TLC1549），DA（TLC5615），232串口，LCD1602接口，LCD12864接口，单片机和CPLD引脚扩展接口，集成5V稳压电源，USB电源接口等功能。 -hhhhhhhhhhhhhhhhhhhhhhhhhhhhh
Platform: |
Size: 194560 |
Author: 胡俊 |
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Description: ad采集的小模块，实现串口转并口的功能，串口是SPI的接口-ad collector modoudle ad ad ad ad ad da da da da shuzi moni moni shuzi caiji caiji caiji caiji caiji caiji caiji
Platform: |
Size: 32768 |
Author: ninglige |
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Description: Die Dateien sind die Sourcen um die Firmware des IDE-CPLD
zu generieren.
Project-Files für die Xilinx-Software habe ich nicht
gespeichert, da diese leicht neu generiert werden kö nnen.
Zuletzt habe ich die Version ISE 8.2 verwendet, aber die
neueren werden wahrscheinlich ä hnlich funktionieren:
Starte die Xilinx Software und beginne ein neues Project
mit dem Project-Wizard:
Device: XC95144XL
Package: TQ144 (TQ100 auf den Hallenbergs Boards)
Speed: -5 (oder was auch immer ihr habt, steht auf dem Chip)-Die Dateien sind die Sourcen um die Firmware des IDE-CPLD
zu generieren.
Project-Files für die Xilinx-Software habe ich nicht
gespeichert, da diese leicht neu generiert werden kö nnen.
Zuletzt habe ich die Version ISE 8.2 verwendet, aber die
neueren werden wahrscheinlich ä hnlich funktionieren:
Starte die Xilinx Software und beginne ein neues Project
mit dem Project-Wizard:
Device: XC95144XL
Package: TQ144 (TQ100 auf den Hallenbergs Boards)
Speed: -5 (oder was auch immer ihr habt, steht auf dem Chip)
Platform: |
Size: 93184 |
Author: mario |
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Description: 基于CPLD的DDS信号发生器，将I2Cflash中的波形数据读出，并将其并行输出，再通过DA转换，得到模拟波形。开发工具是quartusII7.2-The DDS signal generator based on CPLD will I2Cflash the waveform data read out, and its parallel output, and then through the DA converter, are analog waveform. Development tools is quartusII7.2
Platform: |
Size: 838656 |
Author: 朱澄澄 |
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Description: 00IC2407＋CPLD板上选用的DA转换器是TI公司的TLC5620,TLC5620是串行4通道8位
DA 转换器，DSP 通过 SPI 与其接口，TLC5620 的工作频率是 1MHZ,所有 DSP 的 SPI也必须设置位1MHZ, -00IC2407+ CPLD DA converter board is selected TI' s TLC5620, TLC5620 is a serial 4-channel 8-bit DA converters, DSP and its interface, through the SPI, TLC5620 operating frequency is 1MHZ, all the DSP' s SPI must also be set bit 1MHZ,
Platform: |
Size: 67584 |
Author: lizhenli |
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