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[JSP/JavaMipsSimulator

Description: 实现一个具有5段流水线结构的Mips-lite模拟器,该模拟器结构具有data forwarding,stall 处理等功能
Platform: | Size: 285763 | Author: Draco | Hits:

[JSP/JavaMipsSimulator

Description: 实现一个具有5段流水线结构的Mips-lite模拟器,该模拟器结构具有data forwarding,stall 处理等功能-The realization of a pipeline structure with paragraph 5 of the Mips-lite simulator, the simulator structure of data forwarding, stall and other functions to deal with
Platform: | Size: 285696 | Author: Draco | Hits:

[ARM-PowerPC-ColdFire-MIPSmipscpudesign

Description: cpu设计实例mips。MIPSI指令集32位CPU (1)MiniCore设计实例全32位操作,32个32位通用寄存器,所有指令和地址全为32位 (2)静态流水线(3~5级) (3)Forwarding技术 (4)片内L1 Cache,指令、数据各4KByte,硬件初始化 (5)没有TLB,但系统控制协处理器(CP0)具有除页面映射外的全部功能 -cpu design example mips. MIPSI instruction set 32-bit CPU (1) MiniCore design example of the entire 32-bit operation, 32 32-bit general-purpose registers, all the commands and addresses are all 32-bit (2) static line (3 ~ 5) (3) Forwarding technology (4 )-chip L1 Cache, command, data of all 4KByte, hardware initialization (5) there is no TLB, but the system control coprocessor (CP0) with the exception of pages outside the full functionality of mapping
Platform: | Size: 27648 | Author: 游笑 | Hits:

[ARM-PowerPC-ColdFire-MIPSmipssingelcycle

Description: mips single cycle implementation five files auxiliary pc data memory instruction memory adder forwarding
Platform: | Size: 5120 | Author: ramy | Hits:

[VHDL-FPGA-VerilogPipelineCPU

Description: 设计一个32位流水线MIPS微处理器,具体要求如下: 1. 至少运行下列MIPS32指令。 ①算术运算指令:ADD、ADDU、SUB、SUBU、ADDI、ADDIU。 ②逻辑运算指令:AND、OR、NOR、XOR、ANDI、ORI、XORI、SLT、SLTU、SLTI、SLTIU。 ③移位指令:SLL、SLLV、SRL、SRLV、SRA。 ④条件分支指令:BEQ、BNE、BGEZ、BGTZ、BLEZ、BLTZ。 ⑤无条件跳转指令:J、JR。 ⑥数据传送指令:LW、SW。 ⑦空指令:NOP。 2. 采用5级流水线技术,对数据冒险实现转发或阻塞功能。 3. 在XUP Virtex-II Pro开发系统中实现MIPS微处理器,要求CPU的运行速度大于25MHz。-Design a 32-bit pipelined MIPS microprocessor, the specific requirements are as follows: 1. At least run the following MIPS32 instruction. ① arithmetic instructions: ADD, ADDU, SUB, SUBU, ADDI, ADDIU. ② logical operation instructions: AND, OR, NOR, XOR, ANDI, ORI, XORI, SLT, SLTU, SLTI, SLTIU. ③ shift instruction: SLL, SLLV, SRL, SRLV, SRA. ④ conditional branch instruction: BEQ, BNE, BGEZ, BGTZ, BLEZ, BLTZ. ⑤ unconditional jump instruction: J, JR. ⑥ data transfer instruction: LW, SW. ⑦ dummy: NOP. (2) using five pipeline technology, adventure on the forwarding or blocking of data functions. 3 In the XUP Virtex-II Pro development system to achieve MIPS microprocessors, requires the CPU to run faster than 25MHz.
Platform: | Size: 12288 | Author: Peter | Hits:

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