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[Other resource] dcm

Description: 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
Platform: | Size: 10735 | Author: 孙强 | Hits:

[VHDL-FPGA-Verilog] dcm

Description: 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
Platform: | Size: 10240 | Author: 孙强 | Hits:

[SCM] dmc_verilog

Description: 本示例中使用了一个DCM模块，将输入时钟50MHz，倍频到100MHz，分频到25MHz，不同的频率值通过LED进行演示。-This example uses a DCM module, the input clock 50MHz, frequency-doubled to 100MHz, frequency to 25MHz, the frequency of different values demonstrated through the LED.
Platform: | Size: 631808 | Author: 沈天平 | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_controller

Description: DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.-DDR SDRAM controller VHDL source code, including detailed design documents. The DDR, DCM, and SelectI/O
Platform: | Size: 132096 | Author: xbl | Hits:

[Other] DCM

Description: 关于dcm的教材。教你如何使用dcm。非常值得一看哦-Materials on the DCM. Teach you how to use the dcm. Oh, very much worth a visit
Platform: | Size: 621568 | Author: 刘峰 | Hits:

[VHDL-FPGA-Verilog] BUFG_CLK2X_FB_SUBM

Description: xilinx DCM 应用的源代码，完全可用-xilinx DCM application source code, fully available
Platform: | Size: 1024 | Author: 娃娃 | Hits:

[VHDL-FPGA-Verilog] xapp462_vhdl

Description: a example -Code for DCM in language VHDL-a example-Code for DCM in language VHDL
Platform: | Size: 14336 | Author: caoerlin | Hits:

[Documents] DCM

Description: Xilinx公司诸多型号开发版中的一个模块，能够实现1到16次倍频和分频等功能。使用时现在ISE集成开发环境下利用VHDL进行例化。本文档为个人学习总结-Xilinx, a number of models developed version of a module, be able to achieve 1-16 times multiplier and divider functions. ISE now use integrated development environment for the use of VHDL-based cases. This document for personal study and summary
Platform: | Size: 163840 | Author: 张潘睿 | Hits:

[VHDL-FPGA-Verilog] wtut_sc

Description: DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock (CLKIN). The locked output (LOCKED) is high when the two signals are in phase. The signals are considered to be in phase when their rising edges are within a specified time (ps) of each other.
Platform: | Size: 106496 | Author: shad | Hits:

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[Other resource] dcm

[VHDL-FPGA-Verilog] dcm

[SCM] dmc_verilog

[VHDL-FPGA-Verilog] DDR_SDRAM_controller

[Other] DCM

[VHDL-FPGA-Verilog] BUFG_CLK2X_FB_SUBM

[VHDL-FPGA-Verilog] xapp462_vhdl

[Documents] DCM

[VHDL-FPGA-Verilog] wtut_sc

[VHDL-FPGA-Verilog] DCM

[VHDL-FPGA-Verilog] DCM_24M_20M_2M

[VHDL-FPGA-Verilog] Xilinx_DCM

[VHDL-FPGA-Verilog] ledvhd

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