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[VHDL-FPGA-Verilog] ddr2_controller

Description: DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.-DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.
Platform: | Size: 52224 | Author: yanxp | Hits:

[VHDL-FPGA-Verilog] test_ddr2_mem_model

Description: ddr2 test bench top for altera fpga.-ddr2 test bench top for fpga.
Platform: | Size: 4096 | Author: ShengbingChou | Hits:

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