Search - dds MODELSIM

[Other resource] ddsmatlab

Description: dds在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-dds dspbuilder under the VHDL source code and test incentives document matl ab model, the simulation under through modelsim
Platform: | Size: 6896 | Author: zqh | Hits:

[Communication] DDS.RAR

Description: DDS的原理介绍，以一个dds的设计为例，含有modelsim的仿真结果
Platform: | Size: 454920 | Author: dq | Hits:

[VHDL-FPGA-Verilog] 用FPGA实现DDS信号发生及用MODELSIM仿真

Description: 该工程是用verilog编写，FPGA内部产生ROM及ADD加法器。ROM中存正弦波信号。文件夹中还包含modelsim仿真。
Platform: | Size: 2527046 | Author: zhengguo22 | Hits:

[VHDL-FPGA-Verilog] 用modelsim仿真一个正弦波产生程序

Description: 用modelsim仿真一个正弦波产生程序-modelsim simulation using a sine wave generated procedures
Platform: | Size: 68608 | Author: 阿乐 | Hits:

[VHDL-FPGA-Verilog] ddsmatlab

Description: dds在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-dds dspbuilder under the VHDL source code and test incentives document matl ab model, the simulation under through modelsim
Platform: | Size: 6144 | Author: zqh | Hits:

[Program doc] DDS.RAR

Description: DDS的原理介绍，以一个dds的设计为例，含有modelsim的仿真结果-DDS principle introduced in order to design a dds for example, contains a ModelSim simulation results
Platform: | Size: 454656 | Author: dq | Hits:

[VHDL-FPGA-Verilog] FPGA_DDS

Description: 基于FPGA的DDS信号发生器产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-FPGA-based VHDL source DDS signal generator and the test stimulus file matlab model simulation in modelsim adopted under
Platform: | Size: 14486528 | Author: 乐毅学 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 在quartus下的DDS设计，Verilog语言，可以产生正弦波、三角波、方波等，频率可调。-Under the DDS in quartus design, Verilog language, you can produce sine wave, triangle wave, square wave, frequency adjustable.
Platform: | Size: 2632704 | Author: 米多 | Hits:

[VHDL-FPGA-Verilog] FPGAdesignandFIRimplementation

Description: 文档中含有DDS的VHDL实现，FIR滤波器串并FPGA实现，synplify,ISE,ModelSim后仿真流程和FPGA设计的资料-document contains DDS implementation with VHDL , FIR filter serial to parallel and FPGA implementation, and synplify, ISE, ModelSim simulation and FPGA design
Platform: | Size: 1383424 | Author: francis davis | Hits:

[VHDL-FPGA-Verilog] ddsVHDL

Description: fpga设计dds实现调频调相调占空比并用modelsim仿真成功-dds fpga vhdl
Platform: | Size: 6511616 | Author: cc | Hits:

[VHDL-FPGA-Verilog] dds

Description: verilog 硬件语言实现DDS，使用ise11.1和modelsim se6.5仿真测试-verilog hardware language DDS, using the simulation test ise11.1 and modelsim se6.5
Platform: | Size: 2594816 | Author: linzi | Hits:

[VHDL-FPGA-Verilog] dds

Description: DDS数字式频率合成器利用VERILOG实现，有modelsim仿真图-DDS digital frequency synthesizer using VERILOG realization, modelsim simulation diagram
Platform: | Size: 382976 | Author: | Hits:

[VHDL-FPGA-Verilog] ddsfinal1

Description: verilog语言实现的dds代码，并行通信，生成四种波形，大赛编写的代码，modelsim仿真-verilog language dds code,modelsim debug
Platform: | Size: 1137664 | Author: 杨天 | Hits:

[VHDL-FPGA-Verilog] PLL210M

Description: 用VREILOG编写DDS模块 modelsim功能测试通过十分好用-VREILOG to write the DDS module modelsim function test by the very easy to use
Platform: | Size: 3072 | Author: WANGKANG | Hits:

[VHDL-FPGA-Verilog] dds

Description: 在altera的FPGA上实现直接数字频率合成，即用verilog实现DDS，输出正弦波形，在modelsim软件中仿真通过，已包含所有代码和工程以及二进制流文件。-The realization of direct digital frequency synthesis in the Altera FPGA, which is implemented by Verilog DDS, the output sine wave, through the simulation in Modelsim software, already contains all the code and engineering as well as binary stream file.
Platform: | Size: 694272 | Author: 汪少锋 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于 altera cyclone Ⅳ EP4CE30F23C8N的DDS原理、设计方案以及源代码。可以直接考入开发板使用，内含modelsim波形图，方便仿真使用-Based on the principle of altera cyclone Ⅳ EP4CE30F23C8N DDS, design programs and source code. Can be directly admitted to the development board, containing modelsim waveform, easy to use simulation
Platform: | Size: 7305216 | Author: 汪书潮 | Hits:

[VHDL-FPGA-Verilog] DDS(ok)

Description: 制作ROM正弦表并填充FPGA内部ROM，通过调用内部数据实现正弦波输出，开发环境quartusii , 语言verilog , 调试通过，附有modelsim调试结果。-Make ROM sine table and fill the ROM internal FPGA, by calling the internal data to achieve the sine wave output, development environment QuartusII, Language Verilog, debugging through, with Modelsim debugging results.
Platform: | Size: 10149888 | Author: PrudentMe | Hits:

[Other] DDS

Description: FPGA DDS的控制，可以用modelsim直接仿真，观察信号。-DDS of FPGA,able to simulate with modelsim and check the signal
Platform: | Size: 23346176 | Author: terran2831 | Hits:

[Software Engineering] DDS

Description: 分频器，利用quartus软件或者modelsim软件对频率进行分频，也可在硬件上观察出对信号的分频-Frequency divider, quartus software or modelsim software is used to analyse the frequency divider, can also be used on hardware to detect the signal frequency division
Platform: | Size: 1024 | Author: 梁晴 | Hits:

[VHDL-FPGA-Verilog] dds6_ise12migration

Description: 以DE2为开发平台，采用Veriolg语言编程，实现了DDS信号输出，频率，步进，波形输出均可调，采用Modelsim以及FPGA内嵌逻辑分析仪验证设计的正确性，可以满足一定的工程需求。(With DE2 as the development platform and Veriolg language programming, the DDS signal output, frequency, step and waveform output can be adjusted. The correctness of the design is verified by using Modelsim and FPGA embedded logic analyzer, which can meet certain engineering requirements)
Platform: | Size: 3405824 | Author: 小小猪猪猪 | Hits:

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[Other resource] ddsmatlab

[Communication] DDS.RAR

[VHDL-FPGA-Verilog] 用FPGA实现DDS信号发生及用MODELSIM仿真

[VHDL-FPGA-Verilog] 用modelsim仿真一个正弦波产生程序

[VHDL-FPGA-Verilog] ddsmatlab

[Program doc] DDS.RAR

[VHDL-FPGA-Verilog] FPGA_DDS

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] FPGAdesignandFIRimplementation

[VHDL-FPGA-Verilog] ddsVHDL

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] ddsfinal1

[VHDL-FPGA-Verilog] PLL210M

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS(ok)

[Other] DDS

[Software Engineering] DDS

[VHDL-FPGA-Verilog] dds6_ise12migration

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