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[VHDL-FPGA-Verilog] pinglvhecheng

Description: 程序用VHDL实现：频率合成，DDS 主要调用LPM-procedures using VHDL : frequency synthesis, DDS major call LPM
Platform: | Size: 145408 | Author: 刘赛 | Hits:

[VHDL-FPGA-Verilog] ddsall

Description: DDS的vhdl语言源程序实现该程序可实现1HZ频率步进-DDS source VHDL language to achieve the program can be realized 1HZ frequency Step
Platform: | Size: 1024 | Author: 欧阳 | Hits:

[VHDL-FPGA-Verilog] dds_vhdl

Description: dds的vhdl实现,主要包括正弦波、三角波和锯齿波的产生-dds achieve the VHDL, including sine, triangle wave, and the selection ramp
Platform: | Size: 1024 | Author: xxx | Hits:

[VHDL-FPGA-Verilog] ddsVHDL

Description: 基于VHDL的DDS设计，在QUTURS2zhon仿真通过-based on the DDS VHDL design and simulation through the QUTURS2zhon
Platform: | Size: 97280 | Author: wl | Hits:

[VHDL-FPGA-Verilog] ddfs

Description: 我自己用vhdl实现编的dds，能实现正弦波，方波，三角波。-my own use VHDL to achieve series dds, able sine, square, triangle wave.
Platform: | Size: 87040 | Author: 黎明 | Hits:

[VHDL-FPGA-Verilog] dds_quicklogic

Description: 高手写的VHDL源码，实现DDS跳频器功能请大家多提意见-experts write VHDL source code, the frequency-hopping DDS functionality Please speak up
Platform: | Size: 25600 | Author: duyi | Hits:

[Algorithm] 2006-9-21PanWeicaiDDS

Description: 这是一个DDS程序,用VHDL编写,实现的是一个频率可调的方波-This is a DDS procedures, using VHDL prepared achieve is a frequency adjustable square
Platform: | Size: 99328 | Author: dfefe | Hits:

[Embeded-SCM Develop] DDSforsinandcos

Description: 用VHDL实现的DDS，可输出正弦、余弦波形。将所有文件放在一个工程文件里，再分别生存模块，按原理图连接及可-using VHDL DDS, output sine, cosine wave. All documents will be placed on a project document, respectively survival module, according to diagram and can link
Platform: | Size: 7168 | Author: 何明均 | Hits:

[VHDL-FPGA-Verilog] ddssheji

Description: 这是用VHDL语言编写的一个DDS频率合成器的源程序-VHDL prepared a DDS DDS source
Platform: | Size: 975872 | Author: 辛若雪 | Hits:

[VHDL-FPGA-Verilog] DDS_sin

Description: 用VHDL语言实现DDS直接数字频率合成器的设计，采用正弦RAM表，可实现频率可控的正弦数字信号，编译、仿真通过。-VHDL DDS Direct Digital Frequency Synthesizer Design using sinusoidal RAM table achieve controllable frequency sinusoidal digital signal, compile, through simulation.
Platform: | Size: 8192 | Author: sarahyu | Hits:

[VHDL-FPGA-Verilog] DDS_VHDL_xzy

Description: 在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器，芯片是Altera公司的-in EDA software development QuartusII use VHDL DDS signal generator , chip companies are Altera
Platform: | Size: 4760576 | Author: xiaoyong | Hits:

[Other] ddsproject

Description: 用VHDL进行的dds系统设计，包括键盘输入和ＬＣＤ显示，编译通过了-Dds carried out using VHDL system design, including the keyboard and LCD display, the compiler through the
Platform: | Size: 11617280 | Author: 居然 | Hits:

[VHDL-FPGA-Verilog] DDs

Description: 这是我的毕业设计，是用VHDL编程的直接扩频发生器。-This is my graduation project is the use of VHDL programming direct spread-spectrum generator.
Platform: | Size: 459776 | Author: shengm1 | Hits:

[VHDL-FPGA-Verilog] BFSK_VHDL_CODING

Description: 使用DDS技术，应用altera公司的芯片，以及杭州康芯公司的试验箱，实现BFSK信号的调制解调-The use of DDS technology, applications altera chips, as well as the core company in Hangzhou, Culture and Sport chamber, the realization of BFSK signal modulation and demodulation
Platform: | Size: 265216 | Author: 叶峰 | Hits:

[VHDL-FPGA-Verilog] DDS1024

Description: 实现DDS频率可调得VHDL程序，频率步进为1KHZ。包括源程序与仿真程序。-DDS frequency adjustable must realize VHDL procedures, the frequency step for 1KHZ. Including source code and simulation procedures.
Platform: | Size: 238592 | Author: ice | Hits:

[VHDL-FPGA-Verilog] DDS

Description: DDS调试心得,VERIOLG 各HDL和VHDL语言的DDS调试方法-DDS debugging experience, VERIOLG the HDL and VHDL languages DDS debugging method
Platform: | Size: 53248 | Author: 李达兴 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 直接频率合成器，采用verilog hdl-Direct frequency synthesizer using verilog hdl
Platform: | Size: 1024 | Author: 江浩 | Hits:

[VHDL-FPGA-Verilog] DDS-top

Description: 能够基于DDS实现输出正弦波形的一部分程序，利用Verilog HDL语言编写。-Able to achieve based on the DDS output sine wave-shaped part of the procedure, the use of Verilog HDL language.
Platform: | Size: 299008 | Author: evil | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于FPGA的DDS设计，本程序采用verilog HDL语言编写，使用DDS+Pll倍频-The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
Platform: | Size: 190464 | Author: 赵一 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 我们小组共了一个月做的DDS,程序核心用的是Verilog HDL,有仿真波形,输出正弦波,方波,及三角波,步进可调.频率范围1HZ--10MHZ-Our group for a month to do a total of DDS, the procedure is used in the core of Verilog HDL, there are simulation waveform, the output sine wave, square wave and triangular wave, step adjustable. Frequency range 1HZ- 10MHZ
Platform: | Size: 117760 | Author: tiancheng | Hits:

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[VHDL-FPGA-Verilog] pinglvhecheng

[VHDL-FPGA-Verilog] ddsall

[VHDL-FPGA-Verilog] dds_vhdl

[VHDL-FPGA-Verilog] ddsVHDL

[VHDL-FPGA-Verilog] ddfs

[VHDL-FPGA-Verilog] dds_quicklogic

[Algorithm] 2006-9-21PanWeicaiDDS

[Embeded-SCM Develop] DDSforsinandcos

[VHDL-FPGA-Verilog] ddssheji

[VHDL-FPGA-Verilog] DDS_sin

[VHDL-FPGA-Verilog] DDS_VHDL_xzy

[Other] ddsproject

[VHDL-FPGA-Verilog] DDs

[VHDL-FPGA-Verilog] BFSK_VHDL_CODING

[VHDL-FPGA-Verilog] DDS1024

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] DDS-top

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] DDS

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