Search - dds ip

[Other resource] dds

Description: DDs直接数字频率合成器的源代码，其中包括采用IP核和普通两种方式
Platform: | Size: 1378559 | Author: 谭儆轩 | Hits:

[VHDL-FPGA-Verilog] dds

Description: DDs直接数字频率合成器的源代码，其中包括采用IP核和普通两种方式-DDS Direct Digital Synthesizer source code, including the use of IP core and the general two ways
Platform: | Size: 1378304 | Author: 谭儆轩 | Hits:

[VHDL-FPGA-Verilog] 0522

Description: 自己今年的毕业设计DDS波形发生器,有正弦波,方波,三角波,锯齿波.-Their own design this year
Platform: | Size: 1375232 | Author: dawn | Hits:

Description: 此程序在于，调用ISE中自带的DDS__IP，来产生单正弦信号，该程序已通过布线后仿真实现-The program focus on that it utilize the DDS core embedded in the ISE to generate the sigle sinusoid signal and this program have acess to the posted simulation!
Platform: | Size: 1796096 | Author: 艾巍 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: Quartus中实现的DDS 使用的是altera提供的IP core-DDS achieved Quartus using IP core provided by altera
Platform: | Size: 83968 | Author: ray | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 实现函数波形发生器的功能，内有用自己编的源代码实现的，也有用quartus的IP核实现的。-The realization of the function waveform generator function, useful for their own realization of the source code, it also uses the IP core quartus achieved.
Platform: | Size: 1251328 | Author: bluesky428 | Hits:

[Post-TeleCom sofeware systems] qam_64

Description: 64QAM调制,采用硬件语言verilog实现,其中调用了DDS的IP核-64QAM modulation, using language verilog hardware implementation, which is called the IP core of the DDS
Platform: | Size: 1024 | Author: zhujing | Hits:

[VHDL-FPGA-Verilog] MyDDS

Description: 利用查找表法编写的DDS的verilog程序，节省了利用IP核实现需要的资源，软件为ISE，-Prepared using look-up table method of verilog DDS program, save the use of IP core implementation requires resources, software for the ISE,
Platform: | Size: 2891776 | Author: 蜡笔 | Hits:

[VHDL-FPGA-Verilog] dds

Description: dds产生文件源程序，很好用,调用IP核，在ISE中可以使用-dds files generated source code, useful, called IP cores, can be used in the ISE
Platform: | Size: 2048 | Author: wz | Hits:

[VHDL-FPGA-Verilog] dds

Description: 本设计使用8051单片机ip核，并用VHDL语言设计DDS的各功能模块，利用顶层设计的思想组合成DDS（直接数字频率综合）函数信号发生器，并与单片机ip核的I/O口相连。编译完下载到可编程逻辑器件中（FPGA），实现相应的功能。该设计中使用的是LCD2004液晶显示。-dds
Platform: | Size: 2048 | Author: kelas | Hits:

[VHDL-FPGA-Verilog] ISE_lab17

Description: 本实验使用 XILINX 提供的IP 核，并例化该IP 核来实现正弦信号发生器的功能。由于 ISE 中有DDS（Direct Digital Synthesizer 5.0）IP 核，因此只需要编写一个顶层文件来调用 Core Generator 生成的IP 即可。-This study provides the IP core using the XILINX, and cases of the IP core to achieve the sinusoidal signal generator functions. ISE in the DDS (Direct Digital Synthesizer 5.0) IP core, so only need to write a top-level file to call the IP Core Generator can generate.
Platform: | Size: 4096 | Author: | Hits:

[VHDL-FPGA-Verilog] dds

Description: xilinx公司的ddsip核的规格和使用说明，能实现大多数波形的产生。-dds ip core of xilinx company.
Platform: | Size: 1664000 | Author: lucun | Hits:

[VHDL-FPGA-Verilog] DDS

Description: Quartus环境下，使用VHDL语言和IP核进行的通用DDS设计。-Quartus environment, general DDS design using VHDL and IP cores.
Platform: | Size: 1468416 | Author: | Hits:

[VHDL-FPGA-Verilog] dds-dingcengmokuai

Description: ＦＰＧＡ　ＤＤＳ顶层模块基于FPGA的dds ip核的实现，对于学习通信专业的人应该有些帮助-FPGA DDS 顶层模块
Platform: | Size: 5120 | Author: ella | Hits:

[VHDL-FPGA-Verilog] DDS

Description: FPGA产生DDS，未使用IP核，内含VERILOG程序-FPGA generates DDS, unused IP core, containing VERILOG program
Platform: | Size: 585728 | Author: bodao | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于IP核设计的波形发生器以及频率计并用数码管显示-With digital display IP core design based waveform generator and frequency counter
Platform: | Size: 1437696 | Author: 刘铁峰 | Hits:

[DSP program] dds

Description: DDS IP核的使用说明，包括引脚说明和各种波形的仿真图比较-DDS IP core use, including pin description and simulation of various waveforms comparison chart
Platform: | Size: 1661952 | Author: 夏梦月 | Hits:

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[Other resource] dds

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] 0522

[Documents] dds_test

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS

[Post-TeleCom sofeware systems] qam_64

[VHDL-FPGA-Verilog] MyDDS

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] ISE_lab17

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] dds-dingcengmokuai

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS

[DSP program] dds

[Software Engineering] dds

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] dds

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