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[Documents] dds_test

Description: 此程序在于，调用ISE中自带的DDS__IP，来产生单正弦信号，该程序已通过布线后仿真实现-The program focus on that it utilize the DDS core embedded in the ISE to generate the sigle sinusoid signal and this program have acess to the posted simulation!
Platform: | Size: 1796096 | Author: 艾巍 | Hits:

[VHDL-FPGA-Verilog] MyDDS

Description: 利用查找表法编写的DDS的verilog程序，节省了利用IP核实现需要的资源，软件为ISE，-Prepared using look-up table method of verilog DDS program, save the use of IP core implementation requires resources, software for the ISE,
Platform: | Size: 2891776 | Author: 蜡笔 | Hits:

[VHDL-FPGA-Verilog] dds

Description: dds产生文件源程序，很好用,调用IP核，在ISE中可以使用-dds files generated source code, useful, called IP cores, can be used in the ISE
Platform: | Size: 2048 | Author: wz | Hits:

[VHDL-FPGA-Verilog] ISE_lab17

Description: 本实验使用 XILINX 提供的IP 核，并例化该IP 核来实现正弦信号发生器的功能。由于 ISE 中有DDS（Direct Digital Synthesizer 5.0）IP 核，因此只需要编写一个顶层文件来调用 Core Generator 生成的IP 即可。-This study provides the IP core using the XILINX, and cases of the IP core to achieve the sinusoidal signal generator functions. ISE in the DDS (Direct Digital Synthesizer 5.0) IP core, so only need to write a top-level file to call the IP Core Generator can generate.
Platform: | Size: 4096 | Author: | Hits:

[Other Embeded program] sin

Description: 在ISE中用DDS核产生sin函数 可用于信号源的产生、信号的调制-generating sin function using IP CORE DDS in ISE
Platform: | Size: 1024 | Author: hongcan | Hits:

[VHDL-FPGA-Verilog] dual_ram

Description: 在ISE中测试双端口RAM的源码，结合DDS可以通过Isim仿真直接测试RAM IP核的使用是否正常。-Dual-port RAM test source code in ISE, the binding DDS RAM IP core can be directly tested whether the use of the normal simulation.
Platform: | Size: 2048 | Author: 唐宏伟 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 利用ISE中的ip核产生正弦和余弦波形，包含有test测试文件-ISE ip core cosine sine testbench
Platform: | Size: 5760000 | Author: dfdqzp | Hits:

[VHDL-FPGA-Verilog] dds

Description: dds算法，调用xilinx IP ，ise(DDS algorithm, call Xilinx IP, ISE)
Platform: | Size: 5728256 | Author: 阿士大夫 | Hits:

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