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[VHDL-FPGA-Verilognios_dds

Description: 采用Altera的NIOS内核,配合独立的累加器,实现了正弦波,三角波,锯齿波和方波的DDS产生电路,系统时钟最高可达120MHz,配合高速DAC,可产生最高约40MHz左右的波形-Using Altera' s NIOS core, with a separate accumulator, to achieve a sine wave, triangle wave, sawtooth and square wave generation circuit DDS system clock up to 120MHz, with high-speed DAC, can produce up to about 40MHz waveform around
Platform: | Size: 3113984 | Author: Tomy Lee | Hits:

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