Search - des implementation VHDL

Search - des implementation VHDL - List

[matlab] DESHTM DL : 0: 用VHDL语言实现了DES加密算法，其中包含了测试程序，能够进行仿真。-Using VHDL language implementation of the DES encryption algorithm, which contains the test procedures can be simulated.
Update : 2025-03-15 Size : 9kb Publisher : 心飞扬
[VHDL-FPGA-Verilog] DES_IP DL : 0: 有效的改进3-DES算法的执行速度，采用了多级流水线技术，设计了一种高速的硬件结构，使得原来需要48个时钟周期才能完成的运算，现在只需要一个时钟周期就可以完成。另外通过增加输入/输出的控制信号。使得该IP可以方便的集成到SOC中，大大缩短了SOC的设计周期。-Effective 3-DES algorithm to improve the implementation of speed, multi-stage pipeline technology, designed a high-speed hardware architecture, making the original 48 clock cycles required to complete the operation, and now only need one clock cycle can be completed. In addition by increasing the input/output control signal. Makes the IP can be easily integrated into the SOC, the SOC has significantly shortened the design cycle.
Update : 2025-03-15 Size : 23kb Publisher : charity
[VHDL-FPGA-Verilog] DES-HDL DL : 0: 用HDL实现的DES加密算法，通过前仿真，希望对大家有帮助-HDL implementation of the DES with the encryption algorithm, by pre-simulation, we want to help
Update : 2025-03-15 Size : 27kb Publisher : su
[VHDL-FPGA-Verilog] BasicDES DL : 0: The BasicDES Cryptography Core is a small, fast implementation of the DES-56 encryption standard.
Update : 2025-03-15 Size : 26kb Publisher : FPGACore
[Embeded-SCM Develop] FPGA DL : 0: 此课件是基于FPGA的加密芯片设计实例，DES的FPGA实现，包括DES加密算法简述，DES的伪代码描述，设计流程，运算电路模型设计，算法程序设计 -The courseware is based on the FPGA chip design example of encryption, DES for FPGA implementation, including the DES encryption algorithm briefly, DES pseudo-code description of the design process, operation circuit modeling, algorithm programming
Update : 2025-03-15 Size : 3.67mb Publisher : betty
[Software Engineering] des1 DL : 0: 从万方数据库中下的介绍des加密以及解密的两片文章，是用FPGA实现的,pdf格式.希望对理解des加密以及解密的原理有所帮助。 -From the description of the database under the des encryption and decryption of the two articles is the use of FPGA implementation, pdf format. Hope to understand the principles of des encryption and decryption help.
Update : 2025-03-15 Size : 271kb Publisher : chengpan
[VHDL-FPGA-Verilog] 3des_vhdl_latest DL : 0: 3DES的VHDL IP核，64位标准FIPS 46-3 NIST,并且使用3组64位密钥-The VHDL implementation 3DES，The core complies with the Triple-DES 64-bit block cipher defined in FIPS 46-3 NIST standard and operates with three 64-bit keys. Functional Descr
Update : 2025-03-15 Size : 135kb Publisher : XU
[VHDL-FPGA-Verilog] descore_latest.tar DL : 0: VHDL implementation of the classic DES block cipher (interactive architecture)
Update : 2025-03-15 Size : 6kb Publisher : hj