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[VHDL-FPGA-Verilog] DES加密算法的VHDL实现

Description: DES加密算法的VHDL实现,采用流水线技术
Platform: | Size: 17718704 | Author: rungiw | Hits:

[Crack Hack] rom_des

Description: DES 加密算法的VHDL和VERILOG 源程序及其TESTBENCH。-VHDL and VERILOG sourcecode and TESTBENCH of DES encrypting algorithm
Platform: | Size: 30720 | Author: | Hits:

[VHDL-FPGA-Verilog] DES

Description: DES　加密算法的实现，使用硬件描述语言VHDL编写-DES encryption algorithm realization, uses hardware description language VHDL to compile
Platform: | Size: 23552 | Author: zfhustb | Hits:

[VHDL-FPGA-Verilog] tcdg.vhdl

Description: des vhld 源码　程序完成了DES的编码和解码功能-des vhld source procedures completed DES encoding and decoding
Platform: | Size: 5120 | Author: 王亮 | Hits:

[VHDL-FPGA-Verilog] hiervhdl

Description: Using Hierarchy in VHDL Design vhdl语言初学者的天堂-Using VHDL Design VHDL language beginners paradise
Platform: | Size: 44032 | Author: 土木文田 | Hits:

[VHDL-FPGA-Verilog] des.tar

Description: 这是一个vhdl的 DES编程软件,希望大家喜欢 -This is a VHDL programming software DES hope you like
Platform: | Size: 37888 | Author: 沈鹏 | Hits:

[VHDL-FPGA-Verilog] AEScoremodules

Description: AES decoder aes_dec.vhdl AES encoder aes_enc.vhdl Package used by rest of design aes_pkg.vhdl Key Expansion component for AES encoder and decoder key_expansion.vhdl -AES AES encoder decoder aes_dec.vhdl aes_ enc.vhdl Package used by rest of design aes_pkg . vhdl Key Expansion component for a AES encoder nd decoder key_expansion.vhdl
Platform: | Size: 10240 | Author: 许茹芸 | Hits:

[Crack Hack] 3des-VHDL

Description: 3des的VHDL实现，适用于quartus环境-3des VHDL applicable to the environment quartus
Platform: | Size: 95232 | Author: xin | Hits:

[Crack Hack] des

Description: DES加密VHDL源代码,包括速度优先与面积优先两种设计-DES encrypted VHDL source code, including the rate of priority and an area of priority two design
Platform: | Size: 3719168 | Author: wlzpudn | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The examp terms of basic logic gates, to more complex systems, such as a behavioural model of a microprocessor and associated memory. All of the examples can be simulated using any synthesised using current synthesis tools. -This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The exampterms of basic logic gates, to more complex systems, such as a behavioural model of a microprocessor and associated memory. All of the examples can be simulated using anysynthesised using current synthesis tools.
Platform: | Size: 173056 | Author: gbj | Hits:

[VHDL-FPGA-Verilog] 3des_vhdl

Description: 3重DES（3DES）加密算法的问答及其VHDL实现。-3 re-DES (3DES) encryption algorithm and the Q
Platform: | Size: 140288 | Author: 张开文 | Hits:

[Crack Hack] CODE

Description: DES encryption for verilog program
Platform: | Size: 9216 | Author: socketa | Hits:

[Crack Hack] mos_des

Description: 这是一个用VHDL语言实现了DES加密功能的程序，由于DES加密的模式，解密时需把密要倒置-This is a VHDL language with the DES encryption process, as a result of the mode of DES encryption, decryption is required to close to the inverted
Platform: | Size: 27648 | Author: liyajun | Hits:

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[VHDL-FPGA-Verilog] DES加密算法的VHDL实现

[Crack Hack] rom_des

[VHDL-FPGA-Verilog] DES

[VHDL-FPGA-Verilog] tcdg.vhdl

[VHDL-FPGA-Verilog] hiervhdl

[VHDL-FPGA-Verilog] des.tar

[VHDL-FPGA-Verilog] AEScoremodules

[Crack Hack] 3des-VHDL

[Crack Hack] des

[VHDL-FPGA-Verilog] vhdl

[VHDL-FPGA-Verilog] 3des_vhdl

[Crack Hack] CODE

[Crack Hack] mos_des

[VHDL-FPGA-Verilog] DES

[VHDL-FPGA-Verilog] des

[VHDL-FPGA-Verilog] DES

[VHDL-FPGA-Verilog] DES-HDL

[VHDL-FPGA-Verilog] des

[VHDL-FPGA-Verilog] des

[VHDL-FPGA-Verilog] DES

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