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[Other resource] xljc

Description: VHDL的序列检测源代码，ATERA平台下编译通过。附详细说明及仿真源代码。-Sequence Detection VHDL source code, ATERA platform compile. Report detailed description and simulation of the source code.
Platform: | Size: 12619 | Author: 孙彬 | Hits:

[VHDL-FPGA-Verilog] sdh

Description: 帧同步检测源码，包括同步跟踪模块，fifo,分频模块，还有系统的测试平台-frame synchronization source detection, including synchronous tracking module, fifo, frequency module, and system test platform
Platform: | Size: 6144 | Author: liu | Hits:

[Other Embeded program] edge_detector

Description: 基于cpld的数字图像边缘检测算法的实现，vhdl源程序-CPLD-based digital image edge detection algorithm, vhdl source code
Platform: | Size: 1024 | Author: jjaai | Hits:

[Fractal program] videoprocessor

Description: 边沿检测，用vhdl实现sobel算子。-Edge detection, using VHDL realize sobel operator.
Platform: | Size: 8093696 | Author: 大洪 | Hits:

[Software Engineering] Digital_Filter_implementation_by_FPGA

Description: 1.an fpga implementation of the image space reconstruction algorithm for hyperspectral imaging analysis 2. fpga implemention of a median filter 3. fpga implementation of digital filters 4.hardware acceleration of edge detection algorithm on fpgas 5.implementation and evaluation of image processing algorithms on reconfigurable architecture using C-based hardware descriptive languages 6. implementing 2D median filter in fpgas 7.视频图像处理与分析的网络资源
Platform: | Size: 1969152 | Author: carol | Hits:

[VHDL-FPGA-Verilog] edge

Description: 图像处理中边缘检测的VHDL源代码,所用的算法是garbor变换-Image processing edge detection of VHDL source code, the algorithms used are garbor transform
Platform: | Size: 384000 | Author: 翁文天 | Hits:

[Documents] qrsdetection

Description: 在本文中，我们提出了一种新算法，利用重建相图的特征和迟豫坐标去实现QRS波群的实时检测。-In this article, we propose a new algorithm using the characteristics of reconstructed phase portraits by delaycoordinate mapping utilizing lag rotundity for a real-time detection of QRS complexes in ECG signals.
Platform: | Size: 605184 | Author: 牛莉 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: DEMO2 数码管扫描显示电路/DEMO4 计数时钟 DEMO5 键盘扫描设计/DEMO6 波形发生器/DEMO7 用DAC实现电压信号检测/DEMO8 ADC电压测量/DEMO9 液晶驱动电路设计-DEMO2 digital tube display circuit scan/DEMO4 count clock scan design DEMO5 keyboard/DEMO6 Waveform Generator/DEMO7 implementation by DAC voltage signal detection/DEMO8 ADC voltage measurement/DEMO9 LCD driver circuit design
Platform: | Size: 736256 | Author: wang | Hits:

[VHDL-FPGA-Verilog] edge_check2

Description: 一种实用的上升沿检测程序，可用于上升沿检测，或根据上升沿生成高低电平等-Rising edge of a practical testing procedure can be used for rising edge detection, or generated in accordance with the high-low, such as rising edge
Platform: | Size: 1024 | Author: fang | Hits:

[VHDL-FPGA-Verilog] edge_detection

Description: edge detection algorithm in verilog HDL, along with test bench file. compiled in modelsim6.1
Platform: | Size: 34816 | Author: yahyajan | Hits:

[VHDL-FPGA-Verilog] TIMEFACEDETECTIONANDLIPFEATUREEXTRACTIONUSINGFPGA

Description: Abstract—This paper proposes a new technique for face detection and lip feature extraction. A real-time field-programmable gate array (FPGA) implementation of the two proposed techniques is also presented. Face detection is based on a naive Bayes classifier that classifies an edge-extracted representation of an image. Using edge representation significantly reduces the model’s size to only 5184 B, which is 2417 times smaller than a comparable statistical modeling technique, while achieving an 86.6 correct detection rate under various lighting conditions. Lip feature extraction uses the contrast around the lip contour to extract the height and width of the mouth, metrics that are useful for speech filtering. The proposed FPGA system occupies only 15 050 logic cells, or about six times less than a current comparable FPGA face detection system.-Abstract—This paper proposes a new technique for face detection and lip feature extraction. A real-time field-programmable gate array (FPGA) implementation of the two proposed techniques is also presented. Face detection is based on a naive Bayes classifier that classifies an edge-extracted representation of an image. Using edge representation significantly reduces the model’s size to only 5184 B, which is 2417 times smaller than a comparable statistical modeling technique, while achieving an 86.6 correct detection rate under various lighting conditions. Lip feature extraction uses the contrast around the lip contour to extract the height and width of the mouth, metrics that are useful for speech filtering. The proposed FPGA system occupies only 15 050 logic cells, or about six times less than a current comparable FPGA face detection system.
Platform: | Size: 28409856 | Author: ramanaidu | Hits:

[Mathimatics-Numerical algorithms] edge_detection_morphological

Description: edge detection using morphological way..sober and dilation implementation
Platform: | Size: 36864 | Author: sachin | Hits:

[Mathimatics-Numerical algorithms] edge_detector

Description: image edge detection
Platform: | Size: 3072 | Author: sachin | Hits:

[Mathimatics-Numerical algorithms] edgedetect

Description: image edge detection using vhdl
Platform: | Size: 638976 | Author: sachin | Hits:

[Mathimatics-Numerical algorithms] edgewen

Description: edge detection using vhdl
Platform: | Size: 384000 | Author: sachin | Hits:

[VHDL-FPGA-Verilog] FACEDECTION

Description: Real times face detection
Platform: | Size: 3072 | Author: Nam | Hits:

[VHDL-FPGA-Verilog] Edge-detection

Description: 多个边缘检测sobel算子的verilog程序模块。-Multiple edge detection sobel operator verilog program modules
Platform: | Size: 4096 | Author: | Hits:

[VHDL-FPGA-Verilog] FINAL-REPORT

Description: intruder and motion detection system
Platform: | Size: 876544 | Author: sambhuprasad | Hits:

[VHDL-FPGA-Verilog] face-detection

Description: 基于fpga的人脸识别，包括硬件平台的搭建的详细过程，人脸识别算法的详细程序代码。-Fpga-based face recognition, including the hardware platform to build a detailed process of face recognition algorithm detailed code.
Platform: | Size: 432128 | Author: tiger | Hits:

[VHDL-FPGA-Verilog] New-Microsoft-Office-Word-Document

Description: VHDL EDGE DETECTION SYNOPSIS
Platform: | Size: 251904 | Author: aadi | Hits:
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