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[VHDL-FPGA-Verilog] 数字锁相环设计源程序

Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF
Platform: | Size: 120832 | Author: 杰轩 | Hits:

[Post-TeleCom sofeware systems] 数字锁相环dll_code

Description: 通信系统中，信号捕获和同步的数字锁相环的MATLAB仿真程序-communications systems, signal acquisition and synchronization of digital PLL MATLAB simulation program
Platform: | Size: 122880 | Author: zlin | Hits:

[Post-TeleCom sofeware systems] DDScom

Description: 直接式数字锁相环频率合成器.用ELANIX公司SYSTEMVIEW运行.-direct digital PLL frequency synthesizer. SYSTEMVIEW ELANIX companies with operations.
Platform: | Size: 1024 | Author: a | Hits:

[Other] suoxiangyupinluhechengjishu

Description: 锁相与频率合成技术，庄卉等编著。讲述模拟和数字锁相环及频率合成器的理论、组成、测试和设计。-PLL frequency synthesizer with the technology, such as Zhuang Hui edited. On analog and digital PLL frequency synthesizer and the theory, composition, testing and design.
Platform: | Size: 6793216 | Author: Zhou | Hits:

[VHDL-FPGA-Verilog] dpll_demo

Description: 一个实现简单的数字锁相环Verilog代码，本人借鉴网上现有的代码后经修改在Cyclone II上调通实现，里面有ModelSim仿真成功的波形图-A simple digital PLL Verilog code, I draw on-line after the existing code, as amended, pass upward in the Cyclone II realized, there are successful ModelSim Simulation Waveform
Platform: | Size: 67584 | Author: | Hits:

[Communication-Mobile] wb_digital_synthesizer.tar

Description: MIT的一个数字频综源代码，包括cadence的，CPPSIM（MIT做的PLL的设计软件）-MIT, a digital frequency synthesizer source code, including the cadence of, CPPSIM (MIT make the PLL design software)
Platform: | Size: 27648 | Author: hqh | Hits:

[matlab] Matlab_model

Description: 在MATLAB环境下，对全数字锁相环的仿真，分析锁相环的性能参数-In the MATLAB environment, to all-digital phase-locked loop simulation, analysis of the performance parameters of phase-locked loop
Platform: | Size: 243712 | Author: 梁大法 | Hits:

[Documents] The-parameter-design-of-the-digital-phase-lock-loo

Description: 对于如何设计数字PLL的参数很有帮助. 分析了在最小等效噪声带宽，最小相位均方误差，以及最短锁定时间三种意义上的参数优化设计-For how to design the parameters of the digital PLL helpful. Analysis of the minimum noise equivalent bandwidth, minimum-phase mean-square error, as well as the minimum lockout time of three within the meaning of parameter optimization design
Platform: | Size: 82944 | Author: 葭葭 | Hits:

[Software Engineering] PLL

Description: 国外一篇很好的数字锁相环（PLL）设计文档（解压后PLL.pdf），不可不看呦！-Abroad, a good digital phase-locked loop (PLL) design documents (after extracting PLL.pdf), can not look at Yo!
Platform: | Size: 352256 | Author: | Hits:

[Communication-Mobile] PLL

Description: 锁相环问题的仿真，可以解决数字锁相环的仿真问题-Phase-locked loop simulation problem, can solve the problem of digital phase-locked loop simulation
Platform: | Size: 1024 | Author: wangxinyi | Hits:

[VHDL-FPGA-Verilog] 255

Description: 全数字锁相环的Verilog源代码，经过仿真调试-All-digital PLL Verilog source code, through the simulation to debug
Platform: | Size: 154624 | Author: 张文 | Hits:

[Crack Hack] pll

Description: Digital PLL design, all technic how to develope eficiency digital locked loop. All descriptions in English in details and examples
Platform: | Size: 112640 | Author: bugsmenow | Hits:

[VHDL-FPGA-Verilog] 2345676588FPGAxiebofenxi

Description: 本文给出一种基于FPGA的新型谐波检测系统的设计方案。在该方案中，采用FPGA实现快速的FFT运算，采用数字锁相环来同步被测信号，以减小由非同步采样所产生的误差并给出实现的设计实现。数字锁相环和FFT算法用VHDL语言设计实现，该方案能提高谐波分析的精度以及响应速度,同时大大地精简了硬件电路, 系统升级非常方便。-This paper presents a new FPGA-based harmonic detection system design. In the scheme, using the FFT for fast FPGA computing, digital phase-locked loop to synchronize the measured signal to reduce the non-synchronous sampling error arising from implementation of the design and implementation are given. Digital PLL and FFT algorithm design and implementation using VHDL language, the program can improve the accuracy of harmonic analysis and response speed, and greatly streamline the hardware circuit, the system is very easy to upgrade.
Platform: | Size: 18432 | Author: 何正亚 | Hits:

[matlab] Matlabpll

Description: 基于Matlab的数字锁相环的仿真设计，一篇毕业论文，对数字和模拟锁相环进行了详细的分析和仿真-Matlab-based simulation of digital PLL design, a thesis on digital and analog phase-locked loop for a detailed analysis and simulation
Platform: | Size: 199680 | Author: 张鑫 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 数字锁相环电路verilog源代码 开发环境quartus-Digital PLL circuit verilog source code
Platform: | Size: 1024 | Author: louxy | Hits:

[VHDL-FPGA-Verilog] a-new-digital-PLL

Description: 基于FPGA实现的一种新型数字锁相环设计。该设计是用VHDL来实现的，个人觉得不错，所以传上来和大家分享-FPGA-based implementation of a new digital PLL design. The design is to use VHDL to implement the individual feels good, so come and share transfer
Platform: | Size: 181248 | Author: recochun | Hits:

[matlab] Matlab-based-simulation-PLL-design-

Description: 基于Matlab仿真的数字锁相环的设计进行了详细的分析和模拟，数字和模拟锁相环的论文-Matlab-based simulation of digital PLL design, a thesis on digital and analog phase-locked loop for a detailed analysis and simulation
Platform: | Size: 2048 | Author: xufeng | Hits:

[Program doc] digital-PLL

Description: 收集的关于数字锁相环的理论模型和分析讨论，适用于FPGA的数字电路设计。-Theoretical models and analysis and discussion about digital PLL collected for FPGA-based digital circuit design.
Platform: | Size: 18432 | Author: | Hits:

[Communication-Mobile] pll

Description: C++ programm. Digital pll.
Platform: | Size: 1024 | Author: oberon2670 | Hits:

[matlab] pll

Description: 封装的matlab程序，实现数字锁相环的功能函数(Encapsulated matlab program to implement the function function of the digital PLL)
Platform: | Size: 1024 | Author: MFC_B | Hits:
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