Description: 资料中包括了利用凌阳61板和液晶块搭建一个多功能数字电子钟的源码和完整的电路原理图，理论上只要按照指示做，把程序烧进去，就能马上运行。是我一个完整的毕业设计。-Information, including the use of Sunplus 61 boards and blocks to build a multi-function LCD digital clock source and a complete circuit schematic diagram, in theory, as long as in accordance with the instructions, so that burned into the procedure can be run immediately. I graduated from a complete design. Platform: |
Size: 184320 |
Author:曾明 |
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Description: 使用汇编语言实现数字时钟设计，用7seg完成显示，并可以通过button对时钟进行调整。并包括系统仿真原理图，适合做设计者使用-The use of assembly language to achieve digital clock design, with the completion of 7seg show, and can adjust the button on the clock. And includes system simulation schematic diagram, suitable for designers to use Platform: |
Size: 149504 |
Author:wl |
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Description: 一个用8051单片机开发的程序，是带闹钟的数字时钟，含有原理图-8051 with the development of a procedure for the digital clock with alarm, containing schematic Platform: |
Size: 79872 |
Author:李强 |
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Description: 基于CPLD的VHDL语言数字钟（含秒表）设计
利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短（设计过程中即可实现时序仿真）、调试方便、故障率低、修改升级容易等特点。
本设计采用自顶向下、混合输入方式（原理图输入—顶层文件连接和VHDL语言输入—各模块程序设计）实现数字钟的设计、下载和调试。
-CPLD based on the VHDL language digital clock (with stopwatch) design using a chip can be completed in addition to the clock source, buttons, speakers and display (LED) in addition to all functions of digital circuits. All digital logic functions are used in the CPLD device VHDL language. This design has a small and short design cycle (design process to achieve timing simulation), to facilitate debugging, fault rate is low and easy to modify the characteristics of the upgrade. The design uses a top-down, mixed input (input schematic- top-level file access and VHDL language input- the module program design) Design of digital clock, download and debug. Platform: |
Size: 95232 |
Author:wuhuisong |
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Description: 数字时钟 附有程序及原理图 可以直接用 十分方便-Digital clock schematic diagram with the procedures and can be very convenient to use Platform: |
Size: 121856 |
Author:黄立 |
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Description: 完整的数字钟程序，并且附有电路原理图和实物图。希望大家喜欢。-Digital clock complete the procedure, and with a circuit schematic diagram and physical map. I hope you like. Platform: |
Size: 551936 |
Author:禤健 |
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Description: 数字电子钟，和数字贮存式点歌系统的设计，里面附有原理图和源程序，可以运行-Digital electronic clock, and digital storage system design-style song, which with a schematic diagram and source code, you can run Platform: |
Size: 758784 |
Author:zhangbin |
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Description: 这是基于small rtos操作系统的在51系列单片机上实现的一个数字钟，用proteus仿真实现，用原理图，可以在硬件上直接运行，但必须注意要用89S52或者更大ram的芯片。-This is based on small rtos operating system in the 51 series microcontroller implemented on a digital clock, with proteus simulation to achieve, with schematic diagram, you can run directly on hardware, but must pay attention to use 89S52 or greater ram chips. Platform: |
Size: 579584 |
Author:朱信 |
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Description: 基于AT89S52单片机的时钟，用数码管显示，有C程序和原理图-AT89S52 microcontroller based on the clock, with digital display, a C program and schematic Platform: |
Size: 88064 |
Author:亲枝花 |
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Description: 这是多功能数字钟的文档，用Multisim10开发，有原理图以及说明。-This is a multi-functional digital clock document, with Multisim10 development, there is schematic and instructions. Platform: |
Size: 363520 |
Author:莫雨 |
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Description: 任务：
应用一个接口技术设计一个综合键盘和数码管的电子时钟，用键盘控制时钟、修改时间
完成硬件电路原理图的设计
完成软件流程的设计
完成程序清单的设计
要求：
1. 使用8051单片机
2. I/O扩展使用74LS273
3. LED数码管动态显示6位
4. 3*8键盘
5. LED的显示、键盘的扫描用实时中断完成
6. 使用protel绘制电路原理图-Task: The technical design of an interface of an integrated keyboard and digital electronic clock, control the clock with the keyboard, modify the time to complete the design of the hardware circuit diagram of the design process to complete the software design requirements to complete the process list: 1. Using the 8051 2. I/O expansion using the 74LS273 3. LED digital dynamic display 6 4.3* 8 keyboard 5. LED display, keyboard with real-time interrupt the scan to complete 6. using protel schematic drawing Platform: |
Size: 654336 |
Author:庆庆 |
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Description: 数字钟的VHDL源程序，里面附有数字钟的VHDL源程序和原理图的数字钟电路，数字钟有en,clk,clr等接口。-Digital clock in the VHDL source code, which the VHDL source code with a digital clock and schematic of the digital clock circuit digital clock with en, clk, clr and other interfaces.
Platform: |
Size: 603136 |
Author:下世 |
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Description: 数字钟的设计总原理图，使用STC89C52单片机为主控制芯片-Digital clock schematic design of the total, with the main control chip microcontroller STC89C52 Platform: |
Size: 25600 |
Author:董云鹏 |
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Description: 数字时钟，整点报时，有校分校时功能，底层用VHDL，顶层原理图-Digital clock, the whole point of time, when a school campus functions, the bottom with VHDL, top-level schematic Platform: |
Size: 4096 |
Author:1111 |
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Description: 计数器是数字电路系统中最基本的功能模块之一，设计时可以采用原理图或HDL语言完成。
下载验证时的计数时钟可选用连续或单脉冲，并用数码管显示计数值。
-The counter is one of the basic function module in the digital circuit system, can be used in the design of the schematic or HDL language completed. The download validation count clock choice of continuous or single pulse and count value with digital display. Platform: |
Size: 11264 |
Author: |
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Description: 采用AT89S51开发的数字钟程序及原理图，用四位LED数码管显示时间。程序中含LED显示程序及按键处理程序。-Developed using AT89S51 digital clock program and schematic, with four LED digital tube display time. Program buttons with LED display program and processes. Platform: |
Size: 46080 |
Author:应耿宾 |
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Search - digital clock with schematic