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[Program doc] DDS

Description: FPGA中实现基于查找表方式（LUT）的DDS实现，可用在数字下变频和COSTAS锁相环中，Verilog编写，本人已经调通-In FPGA-based lookup table approach (LUT) to achieve the DDS can be used in the digital down-conversion and COSTAS PLL, Verilog prepared, I have transferred Qualcomm
Platform: | Size: 148480 | Author: | Hits:

[VHDL-FPGA-Verilog] dpll_demo

Description: 一个实现简单的数字锁相环Verilog代码，本人借鉴网上现有的代码后经修改在Cyclone II上调通实现，里面有ModelSim仿真成功的波形图-A simple digital PLL Verilog code, I draw on-line after the existing code, as amended, pass upward in the Cyclone II realized, there are successful ModelSim Simulation Waveform
Platform: | Size: 67584 | Author: | Hits:

[VHDL-FPGA-Verilog] 255

Description: 全数字锁相环的Verilog源代码，经过仿真调试-All-digital PLL Verilog source code, through the simulation to debug
Platform: | Size: 154624 | Author: 张文 | Hits:

[VHDL-FPGA-Verilog] pll

Description: quartusII环境下用Verilog语言的数字锁相环的实现。- In quartusII environment digital PLL implementation using Verilog language .
Platform: | Size: 125952 | Author: 刘 | Hits:

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