Search - direct digital synthesizer vhdl

[VHDL-FPGA-Verilog] DDS_sin

Description: 用VHDL语言实现DDS直接数字频率合成器的设计，采用正弦RAM表，可实现频率可控的正弦数字信号，编译、仿真通过。-VHDL DDS Direct Digital Frequency Synthesizer Design using sinusoidal RAM table achieve controllable frequency sinusoidal digital signal, compile, through simulation.
Platform: | Size: 8192 | Author: sarahyu | Hits:

[VHDL-FPGA-Verilog] EDAdesign(3)

Description: 该文件中是关于一些VHDL许多编程实例以及源码分析，希望对VHDL爱好者有用。卷3包括车载DVD位控系统、直接数字频率合成器、图像边缘检测器、等精度数字频率计、出租车计费系统的设计与分析-The document is on a number of VHDL source code in many programming examples and analysis, in the hope that useful VHDL enthusiasts. Car DVD Volume 3 includes digital control system, direct digital frequency synthesizer, image edge detector, such as precision digital frequency meter, taxi Accounting System Design and Analysis
Platform: | Size: 4392960 | Author: shengm1 | Hits:

[VHDL-FPGA-Verilog] FPGAddfs

Description: 基于FPGA的直接数字频率合成器的设计与实现.-FPGA-Based Direct Digital Frequency Synthesizer Design and Implementation.
Platform: | Size: 222208 | Author: 周真 | Hits:

[VHDL-FPGA-Verilog] vhdlddfs

Description: 用VHDL设计直接数字频率合成器-VHDL design with direct digital frequency synthesizer
Platform: | Size: 190464 | Author: 周真 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 直接数字频率合成器，基于vhdl语言，在qartus II上实现，下载调试成功-Direct digital frequency synthesizer, based on the VHDL language, in qartus II achieved a successful download debugging
Platform: | Size: 316416 | Author: 浮云 | Hits:

[VHDL-FPGA-Verilog] dds

Description: DDs直接数字频率合成器的源代码，其中包括采用IP核和普通两种方式-DDS Direct Digital Synthesizer source code, including the use of IP core and the general two ways
Platform: | Size: 1378304 | Author: 谭儆轩 | Hits:

[Wavelet] DDS

Description: 利用EDA技术和FPGA在UP3开发板上实现直接数字频率综合器的设计。实验中加入了相位控制字PWORD，用以控制相位偏移量的前四位，将相位偏移量加到ROM地址总线上，从而引起从ROM中取得的正弦信号的偏移，实现移相信号发生器的移相功能。实验中还加入了LCD显示功能，通过LCD显示模块器件，用LCD显示正弦信号的频率，所显示的频率也是由频率字控制的。LCD的驱动原理同上次实验。-The use of EDA technology and FPGA development in the UP3 board direct digital frequency synthesizer design. Experiment by adding a phase control word PWORD, to control the phase offset of the top four will be added to the phase offset ROM address bus, thereby causing ROM obtained from the sinusoidal signal offset, shifted believe realize its phase-shifting function generator. Experiments have also joined the LCD display, LCD display module through the device, with LCD display the frequency of sinusoidal signal, as shown by the frequency of word frequency control. LCD driving principles with the previous experiment.
Platform: | Size: 1225728 | Author: Emma | Hits:

[VHDL-FPGA-Verilog] EDA

Description: 本章介绍了两个EDA技术的综合应用设计实例:数字闹钟和直接数字频率合成器DDS。-EDA chapter describes the two technologies integrated application design example: digital alarm clock and direct digital synthesizer DDS.
Platform: | Size: 181248 | Author: 黄鹏曾 | Hits:

[VHDL-FPGA-Verilog] DDS_VHDL

Description: 基于FPGA的直接数字频率合成器（DDS）设计（源程序）-FPGA-based direct digital synthesizer (DDS) design (source code)
Platform: | Size: 236544 | Author: jacky | Hits:

[SCM] DDS

Description: 《DDS 原理简介》，DDS即直接数字频率合成器原理简介及系统设计与实现- DDS Principle , DDS direct digital synthesizer Principle and System Design and Implementation
Platform: | Size: 454656 | Author: 范田田 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 《DDS原理简介(中文)》DDS即直接数字频率合成器，原理及系统设计实现- DDS Principle Introduction (Chinese) DDS direct digital frequency synthesizer, the principle and system design to achieve
Platform: | Size: 454656 | Author: 范田田 | Hits:

[VHDL-FPGA-Verilog] FPGA_signal_general

Description: 摘要：介绍了直接数字频率合成 (DDS) 技术的基本原理，给出了基于Altera公司FPGA器件的一个三相正弦信号发生器的设计方案，同时给出了其软件程序和仿真结果。仿真结果表明：该方法生成的三相正弦信号具有对称性好、波形失真小、频率精度高等优点，且输出频率可调。关键词：直接数字频率合成；现场可编程门阵列；FPGA；三相正弦信号-Abstract: Direct Digital Synthesis (DDS) technology, the basic principles are given Altera-based FPGA devices the company a three-phase sinusoidal signal generator design program, at the same time give its software programs and simulation results. The simulation results show that: the method to generate three-phase sinusoidal signal with good symmetry, waveform distortion small, the frequency of high precision, and adjustable output frequency. Key words: direct digital synthesizer field programmable gate array FPGA three-phase sinusoidal signal
Platform: | Size: 101376 | Author: 赵文 | Hits:

[Other] example10

Description: ：正弦波发生器例程，包括了直接数字频率合成(DDS)的原理以及如何应用CPLD产生频率可控频率的正弦信号。-: Sine wave generator routine, including a direct digital synthesizer (DDS), as well as the application of the principle of frequency control CPLD generated sinusoidal signal frequency.
Platform: | Size: 57344 | Author: 周平 | Hits:

[VHDL-FPGA-Verilog] CORDIC

Description: 数字控制振荡器（NCO，numerical controlled oscillator）是软件无线电、直接数据频率合成器（DDS，Direct digital synthesizer）、快速傅立叶变换（FFT，Fast Fourier Transform）等的重要组成部分，同时也是决定其性能的主要因素之一，随着芯片集成度的提高、在信号处理、数字通信领域、调制解调、变频调速、制导控制、电力电子等方面得到越来越广泛的应用。-Digital controlled oscillator (NCO, numerical controlled oscillator) is a software-defined radio, direct data on the frequency synthesizer (DDS, Direct digital synthesizer), Fast Fourier Transform (FFT, Fast Fourier Transform), such as an important component of the decision at the same time the performance of one of the main factors, along with the improvement of the chip integrated in the signal processing, digital communications, modulation and demodulation, frequency conversion speed control, guidance control, such as power electronics get more and more widely.
Platform: | Size: 4096 | Author: 司令 | Hits:

[Other] e

Description: 《EDA技术实用教程》实验选编专题一：计数分频器设计 4 专题二：存储器定制 7 实验一：快速乘法器电路设计 11 实验二：高速数字相关器设计 17 实验三：TLC5510高速A/D转换器控制 21 实验四：直接数字频率合成器（DDFS）设计 23 实验五：基于直接数字频率合成技术的任意波形发生器-" EDA technology practical course" Selected experimental one topic: the design count crossovers feature 4 2: 7 experiment a custom memory: Fast multiplier circuit design of 11 experiments II: the design of high-speed digital correlator 17, the experiment three: TLC5510 high-speed A/D converter control 21 of the experiment four: Direct Digital Frequency Synthesizer (DDFS) experimental design, 23 5: Based on Direct Digital Synthesis technology, arbitrary waveform generator
Platform: | Size: 2693120 | Author: 耿守浩 | Hits:

[VHDL-FPGA-Verilog] FPGA-DDC

Description: 基于FPGA的直接数字频率合成器的设计和实现。-FPGA-Based Direct Digital Frequency Synthesizer Design and Implementation.
Platform: | Size: 100352 | Author: 孙新荣 | Hits:

[VHDL-FPGA-Verilog] ddfsdemo

Description: 直接数字频率合成器（Direct Digital Frequency Synthesizer：DDFS）的VHDL程序,开发环境是QuartusII,系统时钟为50MHz，由PLL产生DDFS的工作时钟166.67MHz,地址位宽为24位，频率字为20，相位字为10，RAM用于存储查找表，其地址位宽为10，数据位宽为8。-Direct Digital Frequency Synthesizer ( DDFS) of the VHDL program, the development environment is QuartusII, the system clock to 50MHz, the work of DDFS generated by PLL clock 166.67MHz, address bit-width of 24-bit frequency word is 20, phase word for 10, RAM used to store look-up table, its address is 10 bits wide, the data is 8 bits wide.
Platform: | Size: 647168 | Author: 力文 | Hits:

[SCM] DDS

Description: 采用DDS实现数字信号发生器, 时钟频率为100MHz,可输出1K到10M的正弦波-use Direct Digital Synthesizer realize SINA wave
Platform: | Size: 8891392 | Author: LiXiuRong | Hits:

[VHDL-FPGA-Verilog] ddfs

Description: 直接数字频率合成器，整个工程文件都在，仿真也有，直接就能用。-Direct digital frequency synthesizer, the entire project file are in the simulation is also directly be able to use.
Platform: | Size: 478208 | Author: 虎 | Hits:

[source in ebook] DDS1-2

Description: 利用FPGA设计一个直接数字频率合成器（DDS），要求能够通过键盘设定输出正弦波、三角波和方波，输出波形频率由键盘输入设定，液晶显示屏显示输出波形类型和频率，输出频率范围10Hz-20kHz，步长0.5Hz。-FPGA design using a direct digital synthesizer (DDS), requires the ability to set the keyboard output sine wave, triangle wave and square wave output waveform frequency from the keyboard input settings, LCD display shows the output waveform type and frequency, output frequency range 10Hz-20kHz, step 0.5Hz.
Platform: | Size: 1855488 | Author: 张箭箭 | Hits:

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[VHDL-FPGA-Verilog] DDS_sin

[VHDL-FPGA-Verilog] EDAdesign(3)

[VHDL-FPGA-Verilog] FPGAddfs

[VHDL-FPGA-Verilog] vhdlddfs

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] dds

[Wavelet] DDS

[VHDL-FPGA-Verilog] EDA

[VHDL-FPGA-Verilog] DDS_VHDL

[SCM] DDS

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] FPGA_signal_general

[Other] example10

[VHDL-FPGA-Verilog] CORDIC

[Other] e

[VHDL-FPGA-Verilog] FPGA-DDC

[VHDL-FPGA-Verilog] ddfsdemo

[SCM] DDS

[VHDL-FPGA-Verilog] ddfs

[source in ebook] DDS1-2

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