Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - div verilog

Search list

[Other resource] div

Description: div的verilog开发程序，做稍微修改就可以应用到具体的工程当中
Platform: | Size: 168490 | Author: 杨华 | Hits:

[Other resource] alu-div

Description: 用verilog HDL代码编写的快速除法器，比较有用
Platform: | Size: 15134 | Author: 徐芬 | Hits:

[VHDL-FPGA-Verilog] div

Description: div的verilog开发程序，做稍微修改就可以应用到具体的工程当中-div of Verilog development process, make a slight modification can be applied to specific projects which
Platform: | Size: 167936 | Author: 杨华 | Hits:

[VHDL-FPGA-Verilog] divider

Description: 基于srt-2算法，利用verilog实现16位定点无符号数除法器（除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成）-Based on the srt-2 algorithm, the use of Verilog to achieve 16-bit unsigned fixed-point divider number (divisor, dividend by 16-bit integer and 16 fractional composition operators from 32-bit integer and 16 fractional composition, the remainder by 32 small array into)
Platform: | Size: 3072 | Author: 刘蒲霞 | Hits:

[VHDL-FPGA-Verilog] alu-div

Description: 用verilog HDL代码编写的快速除法器，比较有用
Platform: | Size: 15360 | Author: 徐芬 | Hits:

[VHDL-FPGA-Verilog] div

Description: 除法器实验 verilog CPLD EPM1270 源代码-Experimental divider verilog CPLDEPM1270 source code
Platform: | Size: 117760 | Author: 韩思贤 | Hits:

[Windows Develop] float_div_verilog

Description: 浮点格式遵循 IEEE754 标准。verilog设计源代码。-float point div . in verilog design.
Platform: | Size: 3072 | Author: gongwen | Hits:

[VHDL-FPGA-Verilog] div

Description: verilog任意分频电路实现，仿真效果非常好-div dclk
Platform: | Size: 413696 | Author: 刘东鑫 | Hits:

[VHDL-FPGA-Verilog] div

Description: 实现了不恢复余数除法器，采用Verilog HDL编码，仿真通过。-Not to restore the balance achieved divider, using Verilog HDL coding, simulation through.
Platform: | Size: 1024 | Author: 张文 | Hits:

[Other] clk_div

Description: 分频计数器verilog源代码,包括实验说明文档,清晰易懂.-this code can easily be understood and teaches you how to divide the clock.
Platform: | Size: 199680 | Author: 颜爱良 | Hits:

[VHDL-FPGA-Verilog] div

Description: 利用Ｖerilog实现定点数的除法，在此基础上可考虑实现定点数的除法-Using Verilog to achieve set division points, on this basis can be considered fixed points of the division to achieve
Platform: | Size: 1024 | Author: 蔡恒 | Hits:

[VHDL-FPGA-Verilog] div

Description: VERILOG除法器，已经调试好。大家可以参照学习.-sub-divided function,I have debug it right.It is helpful to you
Platform: | Size: 129024 | Author: xiaowang | Hits:

[VHDL-FPGA-Verilog] div

Description: 32位整数阵列除法器，verilog代码编写，性能高效。-32-bit integer array divider, verilog coding, performance and efficient.
Platform: | Size: 1024 | Author: Nick | Hits:

[VHDL-FPGA-Verilog] div

Description: restoring divider in verilog
Platform: | Size: 1024 | Author: s.mohammad jazayeri | Hits:

[Other] Div

Description: 非常好用的小数除法器，verilog开发的。quartusii下综合通过-Very easy to use fractional divider, verilog developed. quartusii under comprehensive by
Platform: | Size: 813056 | Author: 洪依 | Hits:

[Other] VerilogFreq-div

Description: Verilog分频程序原理讲解及代码.偶数倍分频奇数倍分频的原理和方法-Verilog divide the program explain the principle and code an even multiple of odd multiple of the principle of divide and divide
Platform: | Size: 6144 | Author: wangfan | Hits:

[VHDL-FPGA-Verilog] div

Description: 两个3位二进制数的除法，结果（整数商）输出到数码管显示-verilog multply
Platform: | Size: 1024 | Author: 晓珊 | Hits:

[Other] div

Description: 这是我用verilog写的一个电平触发的一个除法器，文件在压缩包内，开发环境是Quartus II。-this is a file of divide using verilog language.
Platform: | Size: 1024 | Author: 张浩 | Hits:

[Other] DIV

Description: 用verilog语言设计分屏器，本程序分为两部分，一个可以实现任意奇偶分频的设计，一个可以实现任意半整分频的设计-Split screen using verilog language design, this procedure is divided into two parts, one can achieve arbitrary parity crossover design, one can achieve arbitrary dividing half the whole design
Platform: | Size: 1024 | Author: zhuo | Hits:

[VHDL-FPGA-Verilog] div

Description: FPGA的IP核中除法算法的源代码，是Verilog语言的，易于初学者的学习。-FPGA IP core in the division algorithm source code, Verilog language, easy for beginners to learn.
Platform: | Size: 13312 | Author: leeyoung | Hits:
« 12 »

CodeBus www.codebus.net