Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - div2

Search list

[OS program] div2

Description: 大数除法的实现算法，不仅能实现两个大数的除法，而且能实现浮点数之间以及浮点数与整数之间的除法-majority of the division algorithm, is not only able to make large numbers of division two, but to achieve a float and between integer and floating point divider between the
Platform: | Size: 9257 | Author: 赵惠 | Hits:

[Other resource] div2

Description: 32位除法器 被除数和除数均为16位整数，16位小数 商为32位整数，16位小数 余数为16位整数，16位小数 Verilog HDL 代码
Platform: | Size: 1528 | Author: 李春阳 | Hits:

[Windows Develop] div2 32位除法器

Description: ：32位除法器 被除数和除数均为16位整数，16位小数 商为32位整数，16位小数 余数为16位整数，16位小数 Verilog HDL 代码-32
Platform: | Size: 1532 | Author: hyh110120119@163.com | Hits:

[OS program] div2

Description: 大数除法的实现算法，不仅能实现两个大数的除法，而且能实现浮点数之间以及浮点数与整数之间的除法-majority of the division algorithm, is not only able to make large numbers of division two, but to achieve a float and between integer and floating point divider between the
Platform: | Size: 241664 | Author: 赵惠 | Hits:

[VHDL-FPGA-Verilog] div2

Description: 32位除法器 被除数和除数均为16位整数，16位小数 商为32位整数，16位小数 余数为16位整数，16位小数 Verilog HDL 代码-32 divider dividend and divisor are 16-bit integer, decimal 16 for the 32-bit integer, 16-bit decimal number more than 16 integer, 16-bit decimal Verilog HDL code
Platform: | Size: 1024 | Author: 李春阳 | Hits:

[source in ebook] div2

Description: 分频器（不同分频系数，不同占空比的分频器设计）-Divider
Platform: | Size: 258048 | Author: 紫瓶 | Hits:

[Mathimatics-Numerical algorithms] DIV2

Description: TopCoder上DIV2中一些问题的解答.具体题目见TopCoder的Arena.-some solutions of TopCoder on DIV2 . TopCoder specific topics see the Arena.
Platform: | Size: 48128 | Author: 微蓝 | Hits:

[VHDL-FPGA-Verilog] DIV2

Description: 二分频，占空比，50比50，VHDL语言-Second, frequency, duty cycle, 50 to 50, VHDL language
Platform: | Size: 1024 | Author: 王锋 | Hits:

[VHDL-FPGA-Verilog] odd_division

Description: 实现了时钟奇数（11）分频器，其它奇数分频只要重新计算div1和div2参数就行了。-Realize the clock odd (11) frequency divider, other odd frequency division as long as recount div1 and div2 parameters will do.
Platform: | Size: 30720 | Author: 张明涛 | Hits:

[Algorithm] A

Description: codeforces的ROUND142中div2的A题AC程序。-title of to div2 the A codeforces the ROUND142 AC program.
Platform: | Size: 204800 | Author: lawliet | Hits:

[Algorithm] B

Description: codeforces的ROUND142中div2中的B题AC程序。-B codeforces ROUND142 in div2 in title AC program.
Platform: | Size: 206848 | Author: lawliet | Hits:

[assembly language] div2

Description: DSP源码，定点数除法，实现两个整数的除法，包括完整的工程文件-DSP source code, fixed points of division, two integer division, including complete engineering documents
Platform: | Size: 6144 | Author: Dick | Hits:

[VHDL-FPGA-Verilog] div2

Description: 一种触发器电路的实现方案，效果还可以。速度也比较快。经过方针验证，可以运行。-One kind of flip-flop circuit implementations, the effect can be. Speed 椠猀 relatively fast. After verification guidelines, you can run.
Platform: | Size: 190464 | Author: 远征 | Hits:

[Embeded-SCM Develop] div2

Description: DSP源码，定点数除法，实现两个整数的除法，包括完整的工程文件-DSP source code, fixed points of division, two integer division, including complete engineering documents
Platform: | Size: 6144 | Author: 货单程序 | Hits:

[Embeded-SCM Develop] div2

Description: DSP源码，定点数除法，实现两个整数的除法，包括完整的工程文件-DSP source code, fixed points of division, two integer division, including complete engineering documents
Platform: | Size: 6144 | Author: sionWe | Hits:

CodeBus www.codebus.net