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[VHDL-FPGA-Verilog] 200632146671689

Description: 基于vhdl在FPGA中实现高精度快速除法-based on the FPGA VHDL precision rapid division
Platform: | Size: 741376 | Author: lele | Hits:

[VHDL-FPGA-Verilog] divider

Description: 经过精心设计的除法器的代码，并在FPGA硬件平台实现和验证过的-Meticulously designed divider code, and FPGA hardware platform and tested
Platform: | Size: 1024 | Author: hewg | Hits:

[VHDL-FPGA-Verilog] Chapter6-9

Description: 第六章到第九章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter VI to Chapter IX of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 6281216 | Author: xiao | Hits:

[source in ebook] sanfenpin

Description: verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in the current widespread use of factory-integrated PLL chip resources, such as altera of the PLL, Xilinx' s DLL. to for the sub-clock frequency multiplier and phase shift.
Platform: | Size: 1024 | Author: 杨化冰 | Hits:

[VHDL-FPGA-Verilog] CyclonePLL

Description: Cyclone™ FPGA具有锁相环（PLL）和全局时钟网络，提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出，进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件，就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。 PLL常用于同步内部器件时钟和外部时钟，使内部工作的时钟频率比外部时钟更高，时钟延迟和时钟偏移最小，减小或调整时钟到输出（TCO）和建立（TSU）时间。 -Cyclone ™ FPGA with a phase-locked loop (PLL) and the global clock network and provide a complete clock management solution. Cyclone PLL with the clock multiplier and divider, phase offset, programmable duty cycle and the external clock output for system-level clock management and offset control. Altera ® Quartus ® II software does not require any external devices, you can enable the Cyclone PLL and related functions. This article describes how to design and use the Cyclone PLL features. PLL clock devices commonly used in the synchronization of internal and external clock, so that the inner workings of the clock frequency higher than the external clock, clock delay and clock skew minimum, reduce or adjust the clock to the output (TCO) and the establishment of (TSU) time.
Platform: | Size: 553984 | Author: 裴雷 | Hits:

[VHDL-FPGA-Verilog] Downloads

Description: clock divider in verilog for FPGA use
Platform: | Size: 1024 | Author: harini | Hits:

[VHDL-FPGA-Verilog] clk_divider

Description: Simple Clk Divider for FPGA design in Verilog -Simple Clk Divider for FPGA design in Verilog
Platform: | Size: 1024 | Author: h_j_tel | Hits:

[VHDL-FPGA-Verilog] clock_divider

Description: clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc-clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc
Platform: | Size: 8192 | Author: sreejith | Hits:

[VHDL-FPGA-Verilog] fenpin-FPGA

Description: 本文通过在QuartursⅡ开发平台下，一种能够实现等占空比、非等占空比整数分频及半整数分频的通用分频器的FPGA设计与实现，介绍了利用VHDL硬件描述语言输入方式，设计数字电路的过程。-In this paper, the development platform in Quarturs Ⅱ, one can achieve such duty, such as the duty cycle of non-integer frequency division and semi-integer frequency divider of the FPGA general-purpose design and implementation, describes the use of VHDL hardware description language input , digital circuit design process.
Platform: | Size: 17408 | Author: liu | Hits:

[VHDL-FPGA-Verilog] FPGA-based-multi-Divider

Description: 分频器是指使输出信号频率为输入信号频率1/N的电子电路,N是分频系数。在许多电子设备中如电子钟、频率合成器等，需要各种不同频率的信号协同工作，常用的方法是以稳定度高的晶体振荡器为主振源，通过变换得到所需要的各种频率成分，分频器是一种主要变换手段。 本文当中，在分析研究和总结了分频技术的发展趋势的基础上，以实用、可靠、经济等设计原则为目标，介绍了基于FPGA的多种分频器的设计思路和实现方法。本设计采用EDA技术，以硬件描述语言VHDL为系统逻辑描述手段设计文件，在QuartusⅡ工具软件环境下，采用自顶向下的设计方法，由各个基本模块共同构建了一个基于FPGA的分频器。 本次设计实现了包括整数、半整数和小数这三种不同类型分频器的分频，在设计过程中，系统主芯片采用EP1C6Q240C8，各个模块在QuartusⅡ上进行编程调试和仿真通过后，在GW48-SOPC上进行了下载。通过对各个部分测试后表明均能正确分频，完成了对系统的软件和硬件的设计，达到了系统的设计要求。 -Frequency divider refers to the frequency of the output signal as the input signal 1/N of electronic circuits. N is the frequency coefficient. In many electronic equipments such as the electronic clock, frequency synthesizers, which need different frequency signals work together and common way is to use the stability of the crystal oscillator as vibration source by converting the frequency components all needed. The frequency divider is a major means of conversion. In this paper, with the analytic study and review of trend basis of the technical frequency, a functional, reliable, economic and other design principles as the goal, this paper introduces a number of points frequency of the design and implementation based on FPGA. This design adopts the technology of EDA and hardware description language VHDL as logical description means of designing files. Under the environment of QuartusⅡ tools and the top-to-down approach, they build jointly a frequency divider by the basic modules base
Platform: | Size: 5120 | Author: 吴红梅 | Hits:

[VHDL-FPGA-Verilog] divider

Description: 基于FPGa的32为除法器，从别的地方搞来的，给大家共享以下，算是做贡献。-Divider based on the FPGA 32, to engage in from somewhere else, to share the following to be considered to contribute to.
Platform: | Size: 1024 | Author: 段亚斐 | Hits:

[VHDL-FPGA-Verilog] stopwatch-shuzipabiao

Description: 在FPGA下实现分频、计数、显示功能。 数字跑表-Divider in FPGA, counting and display functions. Digital stopwatch
Platform: | Size: 5120 | Author: 张龙 | Hits:

[VHDL-FPGA-Verilog] Verilog_div_frequency

Description: 本文使用实例描述了在 FPGA/CPLD 上使用 Verilog进行分频器设计，主要包括50 占空比的奇数分频. -This article uses the example describes the crossover design using Verilog in FPGA/CPLD, including the 50 duty cycle odd divider
Platform: | Size: 273408 | Author: 唐阳 | Hits:

[VHDL-FPGA-Verilog] divider

Description: VERILOG编写的24位除法器代码核，是FPGA或者ASIC设计中的一核心计算模块。-VERILOG written 24 divider code nuclear FPGA or ASIC design in a core module.
Platform: | Size: 1024 | Author: Solomon | Hits:

[VHDL-FPGA-Verilog] fenpin

Description: 这是一个二进制的最简单分频器，是一个简短的fpga代码，用verilog书写-This is the most simple of a binary frequency divider, the fpga is a short code, written in verilog
Platform: | Size: 361472 | Author: 燕归梁 | Hits:

[VHDL-FPGA-Verilog] clk1hz

Description: 分频电路 将电路分频为1赫兹 可用于FPGA实验-Frequency divider circuit is a circuit that can be used in FPGA Hz
Platform: | Size: 1024 | Author: Frozen | Hits:

[VHDL-FPGA-Verilog] fixed_pointDivider

Description: 关于定点除法的VHD实现,找了好久，奉献出来大家一起学习！-fixed_point divider is implemented in FPGA .
Platform: | Size: 397312 | Author: 刘苍 | Hits:

[LabView] Design-of-divider

Description: 除法器设计在FPGA板上的应用 除法器设计在FPGA板上的应用-The application of FPGA in design of divider class.
Platform: | Size: 2048 | Author: 高浚玮 | Hits:

[MPI] my_32fp_mult

Description: 这是一个计算32位浮点数的除法器，ALTERA的FPGA可直接用，用VHDL语言写的，希望能帮助有需要的朋友-This is a 32-bit floating-point calculation of divider, ALTERA FPGA can be directly used, written in VHDL language, hoping to help a friend in need
Platform: | Size: 3595264 | Author: jane | Hits:

[Other] divider

Description: a vhdl code for divide operation in fpga spartan6
Platform: | Size: 1408000 | Author: ghanbari1995 | Hits:
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