Search - divider vhdl

[VHDL-FPGA-Verilog] vhdl

Description: RS232数据发送器,适合于VHDL的初学者参考-RS232 data transmitter, suitable for beginners VHDL reference
Platform: | Size: 4096 | Author: 波波 | Hits:

Description: 通过用硬件描述语言（VHDL）描述除法器，并进行模拟验证，加深对二进制数运算方法的理解。设计平台：MaxPlusII 压缩文件内有详细设计报告 -by using Hardware Description Language (VHDL) Description division, and conduct simulation shows that the binary number deepen understanding of the operation. Design Platform : MaxPlusII compressed files with detailed design report
Platform: | Size: 50176 | Author: johnmad | Hits:

[VHDL-FPGA-Verilog] VHDL5

Description: 加法器乘法器电路除法器电路设计键盘扫描电路设计显示电路-Adder multiplier circuit divider circuit design keyboard scan circuit design show circuit, etc.
Platform: | Size: 6144 | Author: | Hits:

[VHDL-FPGA-Verilog] even_divider_VHDL

Description: 常用2、4、6及任意偶数分频器的VHDL代码实现（原创）-used 2,4,6 and even arbitrary divider VHDL code to achieve (original)
Platform: | Size: 1024 | Author: 汤维 | Hits:

[VHDL-FPGA-Verilog] odd_divider_VHDL

Description: 常用1、3、5及任意奇数分频器的VHDL代码实现（原创）-used 1,3,5 and arbitrary odd Divider VHDL code to achieve (original)
Platform: | Size: 1024 | Author: 汤维 | Hits:

[SCM] 9

Description: 本文介绍了两种分频系数为整数或半整数的可控分频器的设计方法。其中之一可以实现50％的奇数分频。利用VHDL语言编程，并用QUARTERS||4.0进行仿真，用 FPGA 芯片实现。关键词：半整数，可控分频器，VHDL, FPGA -This article describes two kinds of sub-frequency coefficient is an integer or half-integer divider controllable design method. One of them can achieve 50 of the odd-numbered sub-frequency. The use of VHDL language programming, and QUARTERS | | 4.0 simulation, using FPGA chip. Key words: semi-integer, controllable divider, VHDL, FPGA
Platform: | Size: 180224 | Author: 陈金豹 | Hits:

[source in ebook] divider

Description: 一个用VHDL语言编写的除法器程序，对从事硬件开发的同志有帮助的。-A language using VHDL divider procedures comrades engaged in hardware development have help.
Platform: | Size: 2048 | Author: maomao | Hits:

[Software Engineering] 353fpga

Description: 用vhdl实现的除法器-Achieved using VHDL divider
Platform: | Size: 1024 | Author: wenhao sun | Hits:

[VHDL-FPGA-Verilog] divider

Description: 此代码用于实现基2的SRT除法器设计，可以实现400MHz以上的32位定点无符号数除法器（除数、被除数和余数均由16位整数和16位小数组成，商由32位整数和16位小数构成,包括源代码和测试文件，可以直接仿真。-This code used to realize the base 2 SRT divider design, you can realize more than 400MHz unsigned 32-bit fixed-point divider number (divisor, dividend and the remainder by the 16-bit integer and 16 fractional composition operators from 32-bit integer and 16 decimal places, including the source code and test files, you can direct simulation.
Platform: | Size: 2048 | Author: 朱秋玲 | Hits:

[VHDL-FPGA-Verilog] divider

Description: 经过精心设计的除法器的代码，并在FPGA硬件平台实现和验证过的-Meticulously designed divider code, and FPGA hardware platform and tested
Platform: | Size: 1024 | Author: hewg | Hits:

[VHDL-FPGA-Verilog] freqdivfinal

Description: 用vhdl实现的分频器，可产生任意对主时钟的分频，从而是实现不同频率pwm的控制-Achieved using VHDL divider can produce any of the sub-master clock frequency, thereby achieving different frequency pwm control
Platform: | Size: 2048 | Author: | Hits:

[Windows Develop] clock-divider

Description: 这是一个关于时钟分频率器的程序，它可以实现频率的扩大。-This is a device on the clock frequency of the procedure, it can realize the expansion of the frequency.
Platform: | Size: 1024 | Author: 李军 | Hits:

[VHDL-FPGA-Verilog] div

Description: 除法器实验 verilog CPLD EPM1270 源代码-Experimental divider verilog CPLDEPM1270 source code
Platform: | Size: 117760 | Author: 韩思贤 | Hits:

[VHDL-FPGA-Verilog] divider

Description: 该模块为分频器，将1KHZ的时钟频率分频成每分钟一次的时钟频率事实上，该源码可以实现任意整数的分频，主要让N的值设置好相应的数字-The module for the divider, the clock frequency 1KHz frequency per minute into the first clock frequency In fact, the source can be any integer frequency, mainly to allow the value of N is set up the corresponding figure
Platform: | Size: 1024 | Author: Tomy Lee | Hits:

[VHDL-FPGA-Verilog] clock_divider

Description: 任意小数分频器产生原理，及详细说明文档，任意数分频(包括奇偶数和小数)的设计方法(含VHDL例子)-Generate arbitrary decimal divider principle, and detailed description of the document, arbitrary number of sub-frequency (including the odd-even numbers and decimals) design methods (including VHDL examples)
Platform: | Size: 23552 | Author: xiang | Hits:

[VHDL-FPGA-Verilog] divider

Description: 移位快速除法器，通过一次移4位试商实现快速除法功能，较普通减除法器有及其巨大的效率提升-Divider rapid shift by a shift to four test functions of rapid division, as compared with ordinary objects have less efficiency and its huge
Platform: | Size: 1024 | Author: jh | Hits:

[VHDL-FPGA-Verilog] FPQ

Description: 分频器的vhdl描述，在源代码中完成对时钟信号CLK的2分频,4分频,8分频,16分频-Divider vhdl description of the source code at the completion of the CLK clock signal frequency of 2 hours, 4 minutes frequency, frequency of 8 hours, 16 minutes frequency
Platform: | Size: 1024 | Author: LS | Hits:

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[VHDL-FPGA-Verilog] vhdl

[VHDL-FPGA-Verilog] 除法器

[VHDL-FPGA-Verilog] VHDL5

[VHDL-FPGA-Verilog] even_divider_VHDL

[VHDL-FPGA-Verilog] odd_divider_VHDL

[SCM] 9

[source in ebook] divider

[Software Engineering] 353fpga

[VHDL-FPGA-Verilog] divider

[VHDL-FPGA-Verilog] divider

[VHDL-FPGA-Verilog] freqdivfinal

[Windows Develop] clock-divider

[VHDL-FPGA-Verilog] div

[VHDL-FPGA-Verilog] divider

[VHDL-FPGA-Verilog] clock_divider

[VHDL-FPGA-Verilog] divider

[VHDL-FPGA-Verilog] FPQ

[VHDL-FPGA-Verilog] divider

[VHDL-FPGA-Verilog] divider

[VHDL-FPGA-Verilog] Divider-vhdl

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