Description: 通过用硬件描述语言（VHDL）描述除法器，并进行模拟验证，加深对二进制数运算方法的理解。
设计平台：MaxPlusII
压缩文件内有详细设计报告
-by using Hardware Description Language (VHDL) Description division, and conduct simulation shows that the binary number deepen understanding of the operation. Design Platform : MaxPlusII compressed files with detailed design report Platform: |
Size: 50176 |
Author:johnmad |
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Description: VHDL 8位无符号除法器 试验报告
计算前在A和B端口输入被除数和除数，然后在Load线上送高电平，把数据存到除法计算电路内部，然后经过若干个时钟周期，计算出商和余数，并在C和D端输出。
其实现方法是，将除法器分为两个状态：等待状态与运算状态。
开始时除法器处于等待状态，在该状态，在每一时钟上升沿，采样Load信号线，若是低电平，则仍处于等待状态，如果采样到高电平，除法器读取A，B数据线上的输入数据，保存到内部寄存器a_r，b_r，置c_r为0，d_r为a_r，判断除数是否为零，若不为零则进入运算状态。
-VHDL eight unsigned divider calculation of the test report before the A and B ports to import and dividend divider, and then sent to I Load line, the data are uploaded to the internal division calculation circuit, and then after a number of clock cycles, and worked out more than a few, and in the C-and D output. Their method is to be divided into two division for the state : waiting for the state and Operational state. At the beginning divider waiting for the state, in the state in each clock rising edge, sampling Load signal line, if low-level, it is still waiting for the state, if the sampling to allow high output, Divider read A, B online data input data, preservation of the internal registers renovation r, b_r, home c_r 0, d_r a_r to determine whether the divisor zero, if not zero, it Platform: |
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Author:aa |
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Description: 这个是用vhdl语言编写的除法器,仅仅供大家参考.-the VHDL language is used to prepare for the division, just for reference. Platform: |
Size: 151552 |
Author:李乐雅 |
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Description: eda7人表决器，设计一个七人表决电路，当参与表决的7人中有4人或4人以上赞同时，表决器输出“1”
表示通过，否则输出“0”表示不通过。
实验时，可用7个电平开关作为表决器的7个输入变量，输入“1”表示表决者“赞同”
输入“0”表示表决者“不赞同”。
-eda7 votes, design a seven-vote circuit, When a vote of seven people who have four or more than four people agree, the division's output "1" indicated, Otherwise output "0" means not through. Experiment, in which seven Level Switches as a vote of seven input variables. the importation of "1", said the vote "endorsed" imported "0" vote, said "do not agree." Platform: |
Size: 10240 |
Author:王哥 |
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Description: 除法器的设计本文所采用的除法原理是：对于八位无符号被除数A，先对A转换成高八位是0低八位是A的数C，在时钟脉冲的每个上升沿C 向左移动一位，最后一位补零，同时判断C的高八位是否大于除数B，如是则C的高八位减去B，同时进行移位操作，将C的第二位置1。否则，继续移位操作。经过八个周期后，所得到的C的高八位为余数，第八位为商。从图(1)可清楚地看出此除法器的工作原理。此除法器主要包括比较器、减法器、移位器、控制器等模块。-Divider design used in this paper, the principle of division is: For the eight unsigned dividend A, the first of A into the high-low 8 0 8 is the A number of C, in each clock rising edge to the left C Mobile One, and finally a zero, at the same time to determine whether C is greater than the high-8 divisor B, so is the high C 8 minus B, at the same time shift operation, the location will be C s second one. Otherwise, continue to shift operation. After eight cycles, received a high C for more than eight the number of eighth place for the business. From Figure (1) can clearly see that the divider works. This mainly includes divider comparators, subtraction, and shifter, controller modules. Platform: |
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Author:lyy |
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Description: 很实用的一个分频带码，包括奇分频，偶分频，占空比为50％的奇分频,实际工程中很实用-Very useful to a sub-band code, including the odd sub-frequency, dual frequency, duty cycle 50 of the odd sub-frequency, the actual works in very practical Platform: |
Size: 290816 |
Author:ecomputer |
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Description: 电子测量技术
ELECTR0NIC MEASI瓜EMENT TECHN0L0GY
第29卷第3期
2006年6月
PS／2设备接口IP核设计
王 豪黄启俊常 胜
(武汉大学物理学院微电子与固体电子学实验室武汉430072)
摘要：用Verilog硬件描述语言实现了PS／2设备接口的II)核设计，详细描述了II)核的结构划分和各模块的
设计思想，并在FPGA上进行验证。结果表明此 核功能正确，可以方便地在SOPC系统中复用。-Electronic Measurement Technology ELECTR0NIC MEASI melon EMENT TECHN0L0GY Vol 29 No. 3 June 2006 PS/2 device interface IP core design黄启俊Changsheng WANG Hao (School of Physics, Wuhan University Microelectronics and Solid State Electronics Laboratory, Wuhan 430072) Abstract: Verilog hardware description language to achieve a PS/2 device interface of II) of nuclear design, described in detail II) the structure of nuclear division and the module Platform: |
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Author:Morgan |
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Description: 数字系统设计基础教程
本书将数字系统作为一个整体的系统，并按层次结构对数字系统进行划分和论述。论题涉及了数字系统技术的各个方面，如：数制、编码、布尔代数、逻辑门、组合逻辑设计、时序电路、VHDL基本概念、VLSI设计基本概念、CMOS逻辑电路和硅芯片、存储器部件、计算机原理和计算机体系结构基础知识等等。本书将传统的数字电路知识和现代技术相结合，适于大专院校相关专业的学生作教科书之用。 -Digital System Design Essentials book digital system as a whole system, together with a hierarchical structure of digital systems division and expositions. Topics related to digital systems in all aspects of technology, such as: the number system, coding, Boolean algebra, logic gates, combinational logic design, sequential circuits, VHDL basic concepts, VLSI design of the basic concepts, CMOS logic circuits and silicon chips, memory components, computer principles and basic knowledge of computer architecture and so on. This book will be a traditional digital circuit knowledge and modern technology, suitable for students of the relevant professional institutions for use in textbooks. Platform: |
Size: 18207744 |
Author:陨星 |
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Description: 通过对于模2除法的研究
可以得到如下方法：
1． 把信息码后面加上p－1位的0，这个试验中p是6位，即在输入的信息码后面加上“00000”。把这个17位的被除数放入input中。
2． 在得到被除数input之后，设计一个在被除数上移动的数据滑块变量d，把input中的最高位开始逐次复制给变量d。
3． 如果d的最高位为1，由变量d和变量p做异或运算；如果d的最高位为0则不运算或者做多余的异或‘0’的运算。
4． 把滑块变量d往后滑动一位。
5． 循环步骤（3，4）11次。
6． 执行步骤3。
7． 得到余数c，把c转成信号输出。
-Through the 2-mode research division will be as follows: 1. Information code followed by the p-1-bit 0, this test p is 6, that is, the information in the input code after 00000. This 17 Add input in the dividend. 2. After receiving input dividend, dividend on the design of a mobile data slider variable d, the highest input in the beginning of successive copied to the variable d. 3. If the highest d for 1, by the variable d and variable p do XOR operations if d the highest computing to 0 or do not redundant XOR 0 arithmetic. 4. The slider sliding variable d next one. 5. Cycle of steps (3,4) 11. 6. Steps 3.7. Be more than a few c, the c into the output signal. Platform: |
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Author:lijq |
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Description: cup 的设计源代码，含有一步乘除法的功能，在fpja上已经测试过。
望对大家有所帮助-cup design source code, which contains step multiplication and division functions in fpja have been tested. We hope to be helpful Platform: |
Size: 870400 |
Author:dong |
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Description: verilog实现的八位CPU，包括乘法、除法以及多种寻址方式。代码中包括测试模块，可以直接在试验箱上运行。-verilog to achieve the eight CPU, including multiplication, division, as well as addressing a variety of ways. Code, including test modules, can be run directly in the chamber. Platform: |
Size: 8192 |
Author:鲁迪 |
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Description: This a program which performs addition,subtraction,multiplication and division of two 4 bit binary numbers..therefore it is called as 4 bit binary ALU..if u have any doubt,then mail me at prem_bombay@yahoo.co.in -This is a program which performs addition,subtraction,multiplication and division of two 4 bit binary numbers..therefore it is called as 4 bit binary ALU..if u have any doubt,then mail me at prem_bombay@yahoo.co.in Platform: |
Size: 1024 |
Author:SUMIT |
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Description: This a simple vhdl code that perform division using the non restoring algorithm which is often handy-This is a simple vhdl code that perform division using the non restoring algorithm which is often handy Platform: |
Size: 1024 |
Author:mma32 |
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Search - division in vhdl