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[VHDL-FPGA-Verilogpci 的vhdl 源代码

Description: pci 的vhdl 源代码-The source code of PCI VHDL.
Platform: | Size: 3072 | Author: 陈旭 | Hits:

[VHDL-FPGA-VerilogDMA_8237A

Description: 经典DMA控制器8237A的VHDL设计,对设计DMA控制器有很高的参考价值。-Classic DMA controller 8237A of the VHDL design, the design of the DMA controller has a high reference value.
Platform: | Size: 12288 | Author: neversee | Hits:

[VHDL-FPGA-VerilogDMA

Description: 针对QUARTUS的DMA的VHDL代码实现-DMA Controller Code in VHDL
Platform: | Size: 2048 | Author: hejian | Hits:

[VHDL-FPGA-Verilogsource

Description: A basic DMA Controller source code
Platform: | Size: 15360 | Author: cadu903 | Hits:

[VHDL-FPGA-VerilogDMA

Description: VHDL code of DMA controller
Platform: | Size: 2048 | Author: Drju | Hits:

[VHDL-FPGA-Verilog8237a

Description: simple dma controller in vhdl
Platform: | Size: 4096 | Author: dyded | Hits:

[VHDL-FPGA-Verilogdma_ahb_latest.tar

Description: this shows the ip code for dma controller of amba ahb in vhdl.
Platform: | Size: 662528 | Author: sachin | Hits:

[VHDL-FPGA-VerilogDMA

Description: DMA controller VHDL code entity dma is generic ( ADDR_WIDTH : integer := 16 -- default value DATA_WIDTH : integer := 16 -- default value ) port ( RESET_L : in std_logic CLK : in std_logic DRQ_L : in std_logic DMAACK_L : in std_logic RDY_L : in std_logic DACK_L : out std_logic DMARQ_L : out std_logic WR_L : inout std_logic ADDR : inout std_logic_vector(ADDR_WIDTH - 1 downto 0) DATA : inout std_logic_vector(DATA_WIDTH - 1 downto 0) ) end dma -DMA controller VHDL code entity dma is generic ( ADDR_WIDTH : integer := 16 -- default value DATA_WIDTH : integer := 16 -- default value ) port ( RESET_L : in std_logic CLK : in std_logic DRQ_L : in std_logic DMAACK_L : in std_logic RDY_L : in std_logic DACK_L : out std_logic DMARQ_L : out std_logic WR_L : inout std_logic ADDR : inout std_logic_vector(ADDR_WIDTH - 1 downto 0) DATA : inout std_logic_vector(DATA_WIDTH - 1 downto 0) ) end dma
Platform: | Size: 2048 | Author: Vlad | Hits:

[ELanguageDma

Description: DMA Controller Code in VHDL
Platform: | Size: 1024 | Author: Alex | Hits:

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