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[Other Embeded program] DPRAM

Description: 网络控制器和链路控制器的CPU即是通过读写双端口RAM芯片完成网络层与数据链路层的原语交互。mailbox中写入的是原语的类型，而双端口RAM的其它存储空间则存放各种服务原语的参数。-network controller and the CPU controller link is through reading and writing dual-port RAM chip to complete the network layer and data link layer of the original language interaction. Mailbox inclusion of the original language is the type of dual-port RAM and the other storage space incorporating various services parameters of the original language.
Platform: | Size: 1024 | Author: 李历 | Hits:

[Embeded-SCM Develop] 双口RAM硬件和软件可靠性握手的实现

Description: 双口RAM硬件和软件可靠性握手的实现 双口RAM硬件和软件可靠性握手的实现-dual-port RAM reliability of the hardware and software to shake hands with the dual port RAM hardware and software to achieve the reliability handshake
Platform: | Size: 97280 | Author: 笑千秋 | Hits:

[Other] allidt_20020616.tar

Description: idt的双口ram的读写接口程序，verilog 代码，并且有测试文档-Employing a dual-port ram reader interface program, Verilog code, and a test document
Platform: | Size: 45056 | Author: | Hits:

[VHDL-FPGA-Verilog] vhdl_ad0809_arm

Description: 本程序是用VHDL语言写的，包括AD0809，双口RAM等程序。已经调试过-this program is written in VHDL, including the AD0809, dual-port RAM, and other procedures. Debugging has been too
Platform: | Size: 4096 | Author: lm | Hits:

[SCM] danpianji3

Description: SH601.C 单片机间的RS232串行通信程序 SH602.C 单片机和PC之间的串行通信程序 SH603.A51 用51单片机的I/O口模拟串口的例程 SH604.C 单片机的无线数据传输例程 SH605.A51 使用单片机实现I2C串行通信的例程 SH606.A51 使用单片机实现的红外数据传输 SH607.C 双端口RAM方式的数据通信例程 608 介绍电平转换芯片MAX485的使用方法和接口电路。 -SH601.C the RS232 serial communication program SH602.C SCM and PC Serial Communication between processes SH603.A51 MCU with 51 I/O Serial the mouth simulation routines SH60 4.C SCM wireless data transmission routines SH605.A51 use MCU I2C serial communication cases Cheng SH606.A51 MCU use of infrared data transmission SH607.C dual-port RAM mode of 608 data communication routines introduced Level Translators MAX485 chip and the use of interface circuit.
Platform: | Size: 60416 | Author: 马一 | Hits:

[Embeded-SCM Develop] dualportRAM

Description: 双端口RAM的VHDL语言实现。完全在CPLD芯片上测试通过。可以实现对存储器读操作的同时对另外一个空间写操作-dual-port RAM VHDL. Totally CPLD chip test. Memory can be achieved right time to operate while the other was a space operation
Platform: | Size: 90112 | Author: 王雪松 | Hits:

[VHDL-FPGA-Verilog] 128×16ram

Description: VHDL程序设计的RAM存储器，双端口，128×16比特-VHDL programming RAM memory, dual-port, 128 × 16 bits
Platform: | Size: 1024 | Author: petri | Hits:

[VHDL-FPGA-Verilog] Asynchronous_read_write_RAM

Description: Dual Port RAM Asynchronous Read/Write 经过modelsim仿真 -Dual Port RAM Asynchronous Read/Write through ModelSim Simulation
Platform: | Size: 1024 | Author: lianlianmao | Hits:

[VHDL-FPGA-Verilog] dul_ram(yk)

Description: 关于双口RAM的Verilog HDL源码-On the dual-port RAM in Verilog HDL source
Platform: | Size: 3072 | Author: 123 | Hits:

[Linux-Unix] dev

Description: linux下 双口ram驱动程序 2.4.18-linux under the dual-port ram driver 2.4.18
Platform: | Size: 4096 | Author: 孙磊 | Hits:

[Embeded-SCM Develop] fifov1

Description: FIFO（先进先出队列）通常用于数据的缓存和用于容纳异步信号的频率或相位的差异。本FIFO的实现是利用 双口RAM 和读写地址产生模块来实现的.FIFO的接口信号包括异步的写时钟（wr_clk）和读时钟（rd_clk）、 与写时钟同步的写有效（wren）和写数据（wr_data） 、与读时钟同步的读有效（rden）和读数据（rd_data） 为了实现正确的读写和避免FIFO的上溢或下溢，给出与读时钟和写时钟分别同步的FIFO的空标志（empty）和 满标志（full）以禁止读写操作。-FIFO (FIFO queue) is usually used for data caching and asynchronous signal used to accommodate the frequency or phase differences. The realization of this FIFO is to use dual-port RAM and to read and write address generator module achieved. FIFO interface signals, including asynchronous write clock (wr_clk) and read clock (rd_clk), and write effectively write clock synchronization (wren) and write data (wr_data), clock synchronization and time effective reading (rden) and read data (rd_data) in order to realize the right to read and write and to avoid FIFO overflow or the underflow, is given with the time clock and write clock synchronization FIFO respectively empty signs (empty) and full logo (full) to prohibit the read and write operations.
Platform: | Size: 378880 | Author: lsg | Hits:

[VHDL-FPGA-Verilog] dualporttst-1_0

Description: xilinx 开发板原程序，双口RAM控制-Xilinx development board the original procedures, dual-port RAM control
Platform: | Size: 195584 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] doubleportram

Description: 高速双端口RAM的vhdl实现。包含仿真波形-High-speed dual-port RAM realize the VHDL. Contains the simulation waveform
Platform: | Size: 303104 | Author: liujingxing | Hits:

[VHDL-FPGA-Verilog] DPRAM

Description: 利用vhdl编写的双端口Ram程序，不带数据纠错处理-VHDL prepared to use dual-port Ram procedures, do not deal with data error correction
Platform: | Size: 1024 | Author: 孙敬辉 | Hits:

[SCM] RAM

Description: 双口RAM的应用-Application of dual-port RAM
Platform: | Size: 168960 | Author: puppy | Hits:

[VHDL-FPGA-Verilog] 13

Description: para13： fifo.vhd FIFO（双口RAM） fifo1.vhd FIFO（嵌入式EAB） fifo2.vhd FIFO（LPM）-para13: fifo.vhd FIFO (dual port RAM) fifo1.vhd FIFO (embedded EAB) fifo2.vhd FIFO (LPM)
Platform: | Size: 3072 | Author: libing | Hits:

[VHDL-FPGA-Verilog] RAM

Description: 双口RAM与PXI总线接口设计，包括接口控制。-Dual-port RAM with PXI bus interface design, including interface control.
Platform: | Size: 1216512 | Author: zwt | Hits:

[VHDL-FPGA-Verilog] ASYNCFIFOXPXMOD

Description: 任意时钟配比的异步fifo.含有synplify ip库中的双端口ram。用于处理多时钟域问题。-Arbitrary ratio of asynchronous clock fifo. Containing synplify ip library of dual-port ram. Used to deal with the issue of multi-clock domain.
Platform: | Size: 5120 | Author: xupeixin | Hits:

[VHDL-FPGA-Verilog] ram_of_Fusion

Description: Fusion中的双口RAM编写，可以实现双向的调用。用Verilog编写。-Fusion in the preparation of dual-port RAM, you can realize a two-way call. Prepared using Verilog.
Platform: | Size: 4096 | Author: Nila | Hits:

[DSP program] dual-ram

Description: 实现双口RAM映射到DSP地址单元空间中，使得双口RAM直接读取DSP中的数据或程序。-Achieve dual-port RAM modules mapped to the DSP address space, making dual-port RAM directly read the data in the DSP or procedures.
Platform: | Size: 2048 | Author: 王正刚 | Hits:
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