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[ELanguage] turbo_VHDL

Description: Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model -Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * M yHDL cycle / bit accurate model * Synthesizable VHDL model
Platform: | Size: 154770 | Author: 鲁京 | Hits:

[Compress-Decompress algrithms] rs_encoder

Description: 一个很不错RS编码，用于DVB的信道编码，用VHDL语言编写，在FPGA上通过验证。
Platform: | Size: 3630 | Author: 杨宇 | Hits:

[VHDL-FPGA-Verilog] frame_sync

Description: 帧同步模块的Veriolog源码。 在ModelSim下的一个工程。有测试文件。-frame synchronization module Veriolog source. The ModelSim of a project. A test document.
Platform: | Size: 24576 | Author: 刘仪 | Hits:

[Communication-Mobile] turbo_VHDL

Description: Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model -Turbo Decoder Release 0.3* Double binary, DVB-RCS code* Soft Output Viterbi Algorithm* M yHDL cycle/bit accurate model* Synthesizable VHDL model
Platform: | Size: 154624 | Author: | Hits:

[Compress-Decompress algrithms] rs_encoder

Description: 一个很不错RS编码，用于DVB的信道编码，用VHDL语言编写，在FPGA上通过验证。-A very good RS encoder for DVB Channel Coding using VHDL language, in the FPGA-validated.
Platform: | Size: 3072 | Author: 杨宇 | Hits:

[Communication] rs_encoder

Description: 此代码是用于DVB系统的信道编码模块，采用（204，188）编码方式，编码后前188个字节是信息位，后16个字节为冗余位。思绪仿真后，通过验证。-This code is used for DVB systems channel coding module (204,188) encoding, after encoding the previous 188 bytes of information, and after the 16-bit byte for redundancy. Simulation thoughts through authentication.
Platform: | Size: 105472 | Author: lilinyan | Hits:

[Windows Develop] ce3100-datasheet

Description: 机顶盒 set top box 设计参考。intel media processor CE 3100 .功能非常强大！-STB set top box reference design. intel media processor CE 3100. very powerful!
Platform: | Size: 1342464 | Author: 姚建平 | Hits:

[Other] RSOriginal

Description: Reed-Solomon 信道编码广泛应用于DVB中-Reed-Solomon channel coding are widely used in DVB
Platform: | Size: 11767808 | Author: 陈孙阳 | Hits:

[Communication] DQPSk

Description:
Platform: | Size: 988160 | Author: deng | Hits:

[Streaming Mpeg4] Channel_coding_of_dvb-t_system

Description: DVB_T系统中信道编码的研究与FPGA实现，一篇很好的说是论文，caj阅读器浏览- Research and FPGA Implementation of Channel Coding in DVB-T Systems
Platform: | Size: 1945600 | Author: bai | Hits:

[Windows Develop] directshow-MUX-DEMUX

Description: H.264解码器ffmpeg完整优化代码包括PC和WindowsMobile版本-ffmpeg WindowsMobile directshow mux implement
Platform: | Size: 361472 | Author: gan yong | Hits:

[Program doc] DVB

Description: DVB系统中交织器和解交织器设计的FPGA实现-DVB system, the reconciliation Interleaver Interleaver design FPGA implementation
Platform: | Size: 708608 | Author: 程钢 | Hits:

[Windows Develop] RANDOMIZATION

Description: DVB 数据随机化程序,标准接口,已应用~!-DVB data randomization procedures, standard interfaces, has been applied ~!
Platform: | Size: 1024 | Author: sun | Hits:

[Windows Develop] SYMBOL_MAPPING

Description: DVB QAM符号映射!已经应用于产品.标准TS流接口-DVB QAM symbol mapping! Has been applied to products. Standard TS stream interface
Platform: | Size: 2048 | Author: sun | Hits:

[VHDL-FPGA-Verilog] CONVOLUTIONAL_INTERLEAVER

Description: DVB数据交织,交织深度I=12,已得到应用!-DVB data interleaving, interleaving depth I = 12, has been applied!
Platform: | Size: 1024 | Author: sun | Hits:

[Program doc] RS3123

Description: Reed- So lomon (RS) 码是一种重要的纠错码, 它对随机性和突发性错误有极强的纠错能力, 广泛应用于 数字视频广播(DVB) 系统和其它数字通信领域。给出了一种GF (25) 域上的RS (31, 23) 编码器的实现算法, 介绍 了用现场可编程门阵列(FPGA ) 实现RS 编码器的原理和过程, 并给出了实现电路及其仿真的输出波形。-Reed-So lomon (RS) code is an important error-correcting code, its random and unexpected error has a strong error correction capabilities, widely used in digital video broadcasting (DVB) systems and other digital communications. Gives a GF (25) Domains RS (31, 23) algorithm of the encoder is introduced with a Field Programmable Gate Array (FPGA) RS encoder to achieve the principles and processes, and providing a circuit and simulation of the output waveform.
Platform: | Size: 360448 | Author: 王彬 | Hits:

[VHDL-FPGA-Verilog] xapp514_aes3-audio

Description: DVB数字音频接口(AESEBU)encoder源码,包括VHDL和VERILOG,基于XILINX FPGA,已验证.-AES-EBU interface,VHDL,VERILOG
Platform: | Size: 4483072 | Author: dcshl | Hits:

[3G develop] turbocodes_latest.tar

Description: 基于sova算法的Turbo码解码VHDL工程文件，非常经典，包含Python高层仿真代码。-Turbo Decoder Release 0.3 MAIN FEATURES - * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model AUTHOR David Brochart <dbrochart@opencores.org>
Platform: | Size: 168960 | Author: John Smith | Hits:

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