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Search - dwt verilog code - List
[
Other resource
]
VHDL_2Ddwt_ALL
DL : 0
這是一個DWT的Verilog code,它的主要功用是PC與FPGA之間的DWT程序的溝通與傳輸
Date
: 2008-10-13
Size
: 1.4mb
User
:
chiahao
[
Wavelet
]
Dwt离散db小波
DL : 0
小波变换子程序-Wavelet Transform Subroutine
Date
: 2025-07-11
Size
: 4kb
User
:
[
VHDL-FPGA-Verilog
]
VerilogHDL
DL : 0
人民邮电出版社<<设计与验证verilog hdl >>一书的配套光盘,包含书上所有原代码,特别是状态机部分,值得学习-Posts
Date
: 2025-07-11
Size
: 1.79mb
User
:
heilongjiang
[
VHDL-FPGA-Verilog
]
VHDL_2Ddwt_ALL
DL : 0
這是一個DWT的Verilog code,它的主要功用是PC與FPGA之間的DWT程序的溝通與傳輸-This is a DWT of the Verilog code, its main function is between the PC and FPGA communication DWT procedures and transmission
Date
: 2025-07-11
Size
: 1.4mb
User
:
chiahao
[
Other Embeded program
]
wavelet_lifting_pld
DL : 0
小波提升Verilog代码,运行于quartusⅡ开发环境。-Wavelet Lifting Verilog code, running on the quartus Ⅱ development environment.
Date
: 2025-07-11
Size
: 484kb
User
:
chalin tong
[
VHDL-FPGA-Verilog
]
verilog
DL : 0
Verilog jpec coder encoder source code
Date
: 2025-07-11
Size
: 277kb
User
:
Martin
[
Wavelet
]
DWT
DL : 0
It s implementation on DWT. This was wrttend in verilog.
Date
: 2025-07-11
Size
: 3kb
User
:
vasantha Kumar
[
Compress-Decompress algrithms
]
DWT
DL : 0
deals with implementation of DWT
Date
: 2025-07-11
Size
: 598kb
User
:
ibbu
[
VHDL-FPGA-Verilog
]
dwt2d_latest[1].tar
DL : 0
小波变换的开源代码(Verilog HDL)包括有测试文件,本人看过,挺好。-code of dwt
Date
: 2025-07-11
Size
: 404kb
User
:
陈先生
[
VHDL-FPGA-Verilog
]
codes
DL : 0
VERILOG CODE FOR DWT IMAGE COMPRESSION
Date
: 2025-07-11
Size
: 16kb
User
:
vijayaragavan
[
Wavelet
]
DWT_xilinx
DL : 0
Dwt(Discrete wavelet transform). verilog code
Date
: 2025-07-11
Size
: 570kb
User
:
Bahu
[
Graph program
]
DWT_verilog-code
DL : 0
图像压缩是图像处理中的一个重要课题,在减少图像尺寸以实时传输和存储方面起着非常重要的作用。许多标准推荐使用DWT进行图像压缩。DWT的计算复杂度对基于DWT的图像压缩算法的实时使用提出了重大挑战。在本文中,我们提出了一种改进的提升方案来计算近似和详细的DWT系数。修正的方程使用右移运算符和6位乘法器。计算中的层级减少到一个,从而最小化延迟和增加吞吐量。ViTEX-5 FPGA上实现的设计工作在180 MHz,功耗小于1W的功率。该设计占用了FPGA上不到1的LUT资源。所开发的体系结构适合于FPGA平台上的实时图像处理。(Image compression is one of the prominent topics in image processing that plays a very important role in reducing image size for real-time transmission and storage. Many of the standards recommend the use of DWT for image compression. The computational complexity of DWT imposes a major challenge for the real-time use of DWT-based image compression algorithms. In this paper, we propose a modified lifting scheme for computing the approximation and detailed coefficients of DWT. The modified equations use, right shift operators and 6-bit multipliers. The hierarchy levels in computation are reduced to one thereby minimizing the delay and increasing throughput. The design implemented on Virtex-5 FPGA operates at 180 MHz and consumes less than 1W of power. The design occupies less than 1 of the LUT resources on FPGA. The architecture developed is suitable for real-time image processing on FPGA platform.)
Date
: 2025-07-11
Size
: 1.41mb
User
:
asde198250
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