Search - emif fpga

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[VHDL-FPGA-Verilog] source_files DL : 0: FPGA与DSP的EMIFA口接口程序.在FPGA内分配了两块双BUFFER与DSP进行通信.-FPGA and DSP EMIFA mouth interface program. The FPGA distribution within the two-SUBJECT ER and DSP communication.
Update : 2025-02-17 Size : 7kb Publisher : tanbo
[DSP program] dsp_5509_EMIF DL : 0: 这个程序是用来配置EMIF的例程。使用时，按readme步骤进行-This procedure is used to the routines EMIF configuration. Use, according to the readme steps
Update : 2025-02-17 Size : 14kb Publisher : 胡楠
[DSP program] DSP_FPGA DL : 0: DSP＋FPGA的实时图像处理硬件系统设计,介绍了两个系统之间的联系-DSP FPGA for real-time image processing hardware system design, describes the links between the two systems
Update : 2025-02-17 Size : 140kb Publisher : yan
[Other] fpgadsp DL : 0: 用于FPGA向DSP传送数据的接口，在硬件上实现需要FPGA的IO口与DSP的地址数据线互连-For the FPGA to the DSP interface to transmit data in the hardware realization of the need for FPGA and DSP of the IO port address data line interconnection
Update : 2025-02-17 Size : 248kb Publisher : 王权
[VHDL-FPGA-Verilog] c_xapp753 DL : 0: 使用 EMIF 将 Xilinx FPGA与 TI DSP 平台接口-EMIF will use Xilinx FPGA and TI DSP platform interface
Update : 2025-02-17 Size : 654kb Publisher : 王大伟
[VHDL-FPGA-Verilog] DSP_EMIF_if DL : 0: fpga开发的程序，内容都不错，主要是top_test-FPGA development process, the contents are good, mainly top_test
Update : 2025-02-17 Size : 1kb Publisher : bob
[VHDL-FPGA-Verilog] 6713emiftofpgatopci DL : 0: 6713emiftofpgatopci,这个是完整的一套从6713的emif到fpga的双口ram，然后主机通过9054到双口ram，交换数据完成-6713emiftofpgatopci, this is a complete set of the EMIF from 6713 to the FPGA
Update : 2025-02-17 Size : 2kb Publisher : 丁科
[VHDL-FPGA-Verilog] EMIFXilinxFPGATIDSP DL : 0: 通过EMIF连接fpga与dsp的代码-Through the EMIF connection FPGA code with dsp
Update : 2025-02-17 Size : 654kb Publisher :
[VHDL-FPGA-Verilog] XilinxisdisclosingthisSpecification DL : 0: Xilinx is disclosing this Specification ? 第 1 章“EMIF 概述”，概述 Texas Instruments EMIF。 ? 第 2 章“Virtex-II 系列或 Spartan-3 FPGA 到 EMIF 的设计”描述将 TI TMSC6000 EMIF 连接到 Virtex?-II 系列或 Spartan?-3 FPGA 的实现。 ? 第 3 章“Virtex-4 FPGA 到 EMIF 的设计” 描述将 TI TMS320C64x EMIF 连接到 Virtex-4 FPGA 的实现。 ? 第 4 章“参考设计” 提供参考设计的目录结构和参考设计文件的链接。 ? 附录 A “Virtex-4 ISERDES 样本代码” 提供 Virtex-4 实现的样本代码列表。 ? 附录 B “EMIF 寄存器域描述” 定义 TI DSP 寄存器域。 ? 附录 C “相关参考文件” 提供相关文档的链接-Xilinx is disclosing this Specification? Chapter 1
Update : 2025-02-17 Size : 654kb Publisher : xujj
[VHDL-FPGA-Verilog] write_io DL : 0: DSP EMIF 扩展io程序 DSP EMIF 扩展io程序-DSP EMIF procedures to expand io expansion io procedures DSP EMIF
Update : 2025-02-17 Size : 92kb Publisher : hanmy
[VHDL-FPGA-Verilog] write_rd DL : 0: 关于VHDL的关于DSP的 emif-On VHDL on the DSP s EMIF
Update : 2025-02-17 Size : 89kb Publisher : hanmy
[Special Effects] video_process_base_on_DSPandFPGA DL : 0: 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管理与算法程序设计彼此分离,并能协同工作. 系统中的图像缓冲区采用了三帧的配置方案,使得该平台最终具有对PAL/ N TSC 两种制式的全分辨率彩色复合视频信号进行实时采集、显示和处理的能力.-Based on high-speed digital signal processor (DSP) and large-scale field programmable gate array (FPGA), successfully developed a smaller, low-power real-time video capture, processing and display platform. One of the DSP is responsible for image processing, all its external digital logic functions are integrated in a FPGA, including high-speed video streaming FIFO, synchronous sequential generate and control, conversion and interface logic for video encoder/decoder to set up the control of nuclear and other I2 C. through increased FIFO bit width, increase the transmission bandwidth, reducing the time occupied by EMIF bus delay phase-locked loop using digital logic,
Update : 2025-02-17 Size : 534kb Publisher : John
[VHDL-FPGA-Verilog] FIFO_EMIF DL : 0: 实现FPGA通过EMIF总线给DSP定期发送数据的功能-FPGA implementation through the EMIF bus regularly send data to the DSP function
Update : 2025-02-17 Size : 1.41mb Publisher : 徐成发
[DSP program] EMIF_COM DL : 0: 实现FPGA与DSP之间通信的接口,利用DSP的标准EMIF接口-the interface for TI DSP and Xilinx s FPGAs
Update : 2025-02-17 Size : 1.09mb Publisher : 贺冲
[DSP program] EMIF DL : 0: A code for dsp6416 in CCSv3.1 that represent the use with EMIF.
Update : 2025-02-17 Size : 276kb Publisher : oleg
[VHDL-FPGA-Verilog] xapp753 DL : 0: FPGA Interface to the TMSC6000 DSP Platform Using EMIF
Update : 2025-02-17 Size : 1.58mb Publisher : jhjkhjnh
[VHDL-FPGA-Verilog] DSP-External-Memory-Interface-Module DL : 0: EMIF是DSP嵌入式系统中重要的外扩接口，往往连接大容量/高速存储器、并行AD/DA、外扩特殊功能芯片，甚至连接FPGA或者ASIC。-EMIF is a DSP embedded system is an important external expansion interface, often connect large-capacity/high-speed memory, parallel AD/DA, outside the extended special function chips, or even connect FPGA ASIC.
Update : 2025-02-17 Size : 56kb Publisher : longdonghuo
[VHDL-FPGA-Verilog] emif DL : 0: fpga emif 通信接口软件设计基于fpga(FPGA EMIF communication interface software design based on FPGA)
Update : 2025-02-17 Size : 1kb Publisher : nbswsin
[Other] 使用 EMIF 将 Xilinx FPGA 与 TI DSP 平台接口 DL : 1: 使用 EMIF 将 Xilinx FPGA 与 TI DSP 平台接口(D:\bootstrap\ce8c548c2a73a823101bfd000ce9d9e3)
Update : 2025-02-17 Size : 654kb Publisher : xxyyzz0
[VHDL-FPGA-Verilog] 国产FPGA参考设计IPCORE_UART_example_M5&M7 DL : 1: 国产FPGA的UART参考设计IPCORE源代码。 The IP provides two kinds of simplified interface connected to EMIF bus and AHB bus for communication with 8051 core and ARM core.The two kinds of interface are full-duplex serial communication interface. Support programmable baud rate Synchronous mode, fixed baud rate 5-bi(The IP provides two kinds of simplified interface connected to EMIF bus and AHB bus for communication with 8051 core and ARM core.The two kinds of interface are full-duplex serial communication interface.)
Update : 2025-02-17 Size : 3.02mb Publisher : 空空居士

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