Search - fft using vhdl

Search - fft using vhdl - List

[VHDL-FPGA-Verilog] FFT的VHDL源代码 DL : 0: FFT的VHDL源代码-fft vhdl source code
Update : 2025-02-17 Size : 29kb Publisher : 阿林
[Other] fft1024ref_v1_0 DL : 0: 用vhdl实现的FFT自电子工程论坛-Achieved using VHDL FFT from electronic engineering Forum
Update : 2025-02-17 Size : 568kb Publisher : zjy
[Linux-Unix] ce05c90f-ada5-4e20-9e6d-80c9b5d8b53c DL : 0: 用vhdl实现的FFT1024点-Achieved using VHDL FFT1024 point
Update : 2025-02-17 Size : 350kb Publisher : zjy
[VHDL-FPGA-Verilog] cfft DL : 0: CFFT是一个数据宽度和点数都可配置的基4 FFT core,用VHDL实现-CFFT is a data width and the base points can be configured 4 FFT core, using VHDL realize
Update : 2025-02-17 Size : 165kb Publisher :
[Algorithm] 20070112201648396 DL : 0: FFT参考设计和一篇用VHDL实现快速傅立叶变换的论文，包括原理分析和代码实现，印度圣雄甘地大学M.A.学院提供 -FFT reference design using VHDL and realize a fast Fourier transform of the thesis, including the principles of analysis and code realize, India Mahatma Gandhi University College, MA
Update : 2025-02-17 Size : 91kb Publisher : 吴庆庆
[VHDL-FPGA-Verilog] FFT_report DL : 0: Design Simulation and synthesis of a fft processor using VHDL
Update : 2025-02-17 Size : 354kb Publisher : lys
[VHDL-FPGA-Verilog] fft_test DL : 0: 用vhdl编写的FFT的代码,很全,很强大.-FFT prepared using VHDL code, it is wide, it is powerful.
Update : 2025-02-17 Size : 891kb Publisher : fangyingjie
[Algorithm] FFT(VHDL) DL : 0: 数字信号处理fft算法计算，用fpga开发，vhdl语言写成-Digital signal processing fft algorithm using FPGA development, vhdl language
Update : 2025-02-17 Size : 14kb Publisher : 程钢
[matlab] fft DL : 0: fft代码,采用蝶形算法,包括C,matlab和verilog代码-fft code, using butterfly algorithm, including C, matlab and Verilog code
Update : 2025-02-17 Size : 46kb Publisher : 陈
[VHDL-FPGA-Verilog] fftipcore DL : 0: 实现fft的ip核，用vhdl语言实现。-Fft realize the ip nuclear, using VHDL language.
Update : 2025-02-17 Size : 31kb Publisher : liu
[VHDL-FPGA-Verilog] cf_fft_1024_8 DL : 0: 用verilog编写的1024点的fft快速傅立叶变换-Verilog prepared using 1024 point fft Fast Fourier Transform
Update : 2025-02-17 Size : 11kb Publisher : xlxiaoling
[VHDL-FPGA-Verilog] FFT-FPGA DL : 0: FFT处理器的FPGA设计方法，适合做信号处理的技术人员参考，用FPGA实现-FFT processor, FPGA design, suitable for signal processing technology for reference, using FPGA to achieve
Update : 2025-02-17 Size : 200kb Publisher : bonjour
[VHDL-FPGA-Verilog] VHDL_FFT1 DL : 0: 基于FPGA设计的FFT模块文件，用VHDL语言编写！！已通过测试，希望对大家有用-FFT designs based on FPGA module file, using VHDL language! ! Has passed the test, hope for all of us! ! !
Update : 2025-02-17 Size : 29kb Publisher : 林海
[VHDL-FPGA-Verilog] VHDL_FFT2 DL : 0: 基于FPGA设计的FFT模块文件，用VHDL语言编写！！已通过测试，希望对大家有用-FFT designs based on FPGA module file, using VHDL language! ! Has passed the test, hope for all of us! ! !
Update : 2025-02-17 Size : 13kb Publisher : 林海
[VHDL-FPGA-Verilog] fft_gen DL : 0: FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results. here is what I do: 1- from core generator I choose fft core and create .vhd & .vho & .xco files. 2- I add the .xco & .vhd files to my project. 3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.-FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results. here is what I do: 1- from core generator I choose fft core and create .vhd & .vho & .xco files. 2- I add the .xco & .vhd files to my project. 3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.
Update : 2025-02-17 Size : 6kb Publisher : Jayesh
[VHDL-FPGA-Verilog] FFT DL : 0: fft implementation in fpga using vhdl xilinx
Update : 2025-02-17 Size : 874kb Publisher : prabin
[Software Engineering] RADIX_64 DL : 0: radix 64 point fft using vhdl design in fpga
Update : 2025-02-17 Size : 124kb Publisher : bowya
[VHDL-FPGA-Verilog] 2345676588FPGAxiebofenxi DL : 0: 本文给出一种基于FPGA的新型谐波检测系统的设计方案。在该方案中，采用FPGA实现快速的FFT运算，采用数字锁相环来同步被测信号，以减小由非同步采样所产生的误差并给出实现的设计实现。数字锁相环和FFT算法用VHDL语言设计实现，该方案能提高谐波分析的精度以及响应速度,同时大大地精简了硬件电路, 系统升级非常方便。-This paper presents a new FPGA-based harmonic detection system design. In the scheme, using the FFT for fast FPGA computing, digital phase-locked loop to synchronize the measured signal to reduce the non-synchronous sampling error arising from implementation of the design and implementation are given. Digital PLL and FFT algorithm design and implementation using VHDL language, the program can improve the accuracy of harmonic analysis and response speed, and greatly streamline the hardware circuit, the system is very easy to upgrade.
Update : 2025-02-17 Size : 18kb Publisher : 何正亚
[VHDL-FPGA-Verilog] IMPLEMENTATION-OF-FFT-USING-VHDL DL : 0: it is the document which will help in implementing vhdl fft
Update : 2025-02-17 Size : 354kb Publisher : tinku
[Documents] FFT-using-VHDL DL : 0: fft using vhdl document
Update : 2025-02-17 Size : 976kb Publisher : kiranraj tak

« 12 3 »